LC88F40H0PA Datasheet, PDF (22/32 Pages) Sanyo Semicon Device – For Car Audio Systems 16-bit ETR Microcontroller

LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Continued from preceding page.
Parameter
Data hold time
Symbol
tHD; DAT
tHD; DATx
Applicable Pin
/Remarks
SM0CK(P22)
SM1CK(PA0)
SM2CK(PA3)
SM3CK(P75)
SM0DA(P23)
SM1DA(PA1)
SM2DA(PA4)
SM3DA(P76)
Conditions
• See fig. 2.
VDD[V]
VDDPORT=
• Specified as interval up to time
VDD(1) to 5.5
when output state starts changing.
Specification
min
typ max
unit
0
Tfilt
1
1.5
Data setup time
tSU; DAT
SM0CK(P22) • See fig. 2.
SM1CK(PA0)
1
SM2CK(PA3)
tSU; DATx
SM3CK(P75)
SM0DA(P23)
• Specified as interval up to time
VDDPORT=
VDD(1) to 5.5
Tfilt
SM1DA(PA1)
when output state starts changing.
1tSCL
SM2DA(PA4)
-1.5Tfilt
SM3DA(P76)
Fall time
tF
SM0CK(P22) • See fig. 2.
SM1CK(PA0)
VDDPORT=
300
SM2CK(PA3)
VDD(1) to 5.5
tF
SM3CK(P75) _{• When SMIIC register control bits,}
SM0DA(P23)
PSLW=1, P5V=1
VDDPORT=5 20+0.1Cb
250
SM1DA(PA1) _{• When SMIIC register control bits,}
ns
SM2DA(PA4) _{PSLW=1, P5V=0}
VDDPORT=3 20+0.1Cb
250
SM3DA(P76) _{• When SMIIC register control bits,}
PSLW=0
VDDPORT=
100
• Cb ≤ 400pF
VDD(1) to 5.5
Note 4-6-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-6-2: The value of Tfilt is determined by the values of the register SMICnBRG (n=0, 1, 2, 3), bits 7 and 6 (BRP1,
BRP0) and the system clock frequency.
BRP1
BRP0
Tfilt
0
0
tCYC × 1
0
1
tCYC × 2
1
0
tCYC × 3
1
1
tCYC × 4
Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range:
250ns ≥ Tfilt > 140ns
Note 4-6-3: Cb represents the total loads (in pF) connected to the bus pins. Cb ≤ 400pF
Note 4-6-4: The standard-mode refers to a mode that is entered by configuring SMICnBRG (n=0, 1, 2, 3) as follows:
250ns ≥ Tfilt > 140ns
BRDQ (bit5) = 1
SCL frequency setting ≤ 100kHz
The fast-mode refers to a mode that is entered by configuring SMICnBRG (n=0, 1, 2, 3) as follows:
250ns ≥ Tfilt > 140ns
BRDQ (bit5) = 0
SCL frequency setting ≤ 400kHz
No.A1853-22/32