LC88F40H0PA Datasheet, PDF (18/32 Pages) Sanyo Semicon Device – For Car Audio Systems 16-bit ETR Microcontroller

LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
Continued from preceding page.
Parameter
Symbol
Applicable Pin
/Remarks
Pin capacitance CP
All pins
Low voltage
circuit
detection
voltage
VDET(1) VDDCPU
VDET(2) VDDCPU
Conditions
• For pins other than that under
test: VIN=VSS
• f=1MHz
• Ta=25°C
On low voltage detection circuit
Excluding the HOLD mode
On low voltage detection circuit
HOLD mode
VDD[V]
Specification
min
typ
max
unit
10
pF
2.7
2.85
3.0
V
1.27
1.42
1.57
V
Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
1. SIO0, SIO1 Serial I/O Characteristics (Wakeup Function Disabled) (Note 4-1-1)
Parameter
Period
Low level
pulse width
High level
pulse width
Period
Low level
pulse width
High level
pulse width
Data setup time
Data hold time
Symbol
tSCK(1)
tSCKL(1)
tSCKH(1)
tSCKHA(1)
tSCKHBSY
(1a)
tSCKHBSY
(1b)
tSCK(2)
tSCKL(2)
tSCKH(2)
tSCKHA(2)
tSCKHBSY
(2a)
tSCKHBSY
(2b)
tsDI(1)
thDI(1)
Applicable Pin
/Remarks
Conditions
SCK0(P12) • See Fig. 1.
SCK1(P45)
SCK0(P12)
SCK1(P45)
• Automatic communication mode
• See Fig. 1.
• Automatic communication mode
• See Fig. 1.
• Modes other than automatic
communication mode
• See Fig. 1.
• CMOS output selected
• See Fig. 1.
SIO0(P11),
SIO1(P44)
• Automatic communication mode
• CMOS output selected
• See Fig. 1.
• Automatic communication mode
• CMOS output selected
• See Fig. 1.
• Modes other than automatic
communication mode
• See Fig. 1.
• Specified with respect to rising
edge of SIOCLK
• See fig. 1.
VDD[V]
VDDPORT=
VDD(1) to 5.5
VDDPORT=
VDD(1) to 5.5
VDDPORT=
VDD(1) to 5.5
min
4
2
2
6
23
4
4
6
4
4
0.03
0.03
Specification
typ
max
unit
tCYC
1/2
tSCK
1/2
23 tCYC
Output
delay time
tdD0(1)
tdD0(2)
SO0(P10),
SO1(P43),
SIO0(P11),
SIO1(P44)
• (Note 4-1-2)
• (Note 4-1-2)
VDDPORT=
VDD(1) to 5.5
1tCYC μs
+0.05
1tCYC
+0.05
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: Specified with respect to falling edge of SIOCLK. Specified as the time to the beginning of output state
change in open drain output mode. See Fig. 1.
No.A1853-18/32