LC88F40H0PA Datasheet, PDF (21/32 Pages) Sanyo Semicon Device – For Car Audio Systems 16-bit ETR Microcontroller

LC88F40H0PA/H0PAU/F0PA/F0PAU/D0PA/D0PAU
4. SMIIC0 to SMIIC3 I²C Mode Input/Output Characteristics
Parameter
Period
Symbol
tSCL
Low level
pulse width
High level
pulse width
tSCLL
tSCLH
Applicable Pin
/Remarks
SM0CK(P22)
SM1CK(PA0)
SM2CK(PA3)
SM3CK(P75)
Conditions
• See Fig. 2.
VDD[V]
VDDPORT=
VDD(1) to 5.5
min
5
2.5
2
Period
tSCLx
SM0CK(P22) • Specified as interval up to time
10
SM1CK(PA0) when output state starts changing.
Low level
pulse width
High level
tSCLLx
tSCLHx
SM2CK(PA3)
SM3CK(P75)
VDDPORT=
VDD(1) to 5.5
pulse width
SM0C and SM0DA
tsp
SM0CK(P22) • See fig. 2.
pins input spike
suppression time
SM1CK(PA0)
SM2CK(PA3)
SM3CK(P75)
SM0DA(P23)
SM1DA(PA1)
SM2DA(PA4)
SM3DA(P76)
Bus release
tBUF
SM0CK(P22) • See fig. 2.
time between
SM1CK(PA0)
2.5
start and stop
SM2CK(PA3)
tBUFx
SM3CK(P75)
SM0DA(P23) ^{• Standard-mode}
VDDPORT=
SM1DA(PA1) ^{• Specified as interval up to time}
VDD(1) to 5.5
5.5
SM2DA(PA4)
when output state starts changing.
SM3DA(P76) ^{• Fast-mode}
• Specified as interval up to time
1.6
when output state starts changing.
Start/restart
condition hold
time
tHD; STA
SM0CK(P22) • When SMIIC register control bit,
SM1CK(PA0) I2CSHDS=0
2.0
SM2CK(PA3) • See fig. 2.
SM3CK(P75) _{• When SMIIC register control bit,}
SM0DA(P23)
I2CSHDS=1
2.5
SM1DA(PA1) _{• See fig. 2.}
VDDPORT=
tHD; STAx
SM2DA(PA4) _{• Standard-mode}
VDD(1) to 5.5
SM3DA(P76) _{• Specified as interval up to time}
4.1
when output state starts changing.
• Fast-mode
• Specified as interval up to time
1.0
when output state starts changing.
Restart
condition setup
time
tSU; STA
SM0CK(P22) • See fig. 2.
SM1CK(PA0)
1.0
SM2CK(PA3)
tSU; STAx
SM3CK(P75) _{• Standard-mode}
SM0DA(P23) _{• Specified as interval up to time}
VDDPORT=
5.5
SM1DA(PA1)
when output state starts changing. ^{VDD(1) to 5.5}
SM2DA(PA4) _{• Fast-mode}
SM3DA(P76) _{• Specified as interval up to time}
1.6
when output state starts changing.
Stop condition
setup time
tSU; STO
SM0CK(P22) • See fig. 2.
SM1CK(PA0)
1.0
SM2CK(PA3)
tSU; STOx
SM3CK(P75) _{• Standard-mode}
SM0DA(P23) _{• Specified as interval up to time}
VDDPORT=
4.9
SM1DA(PA1)
when output state starts changing. ^{VDD(1) to 5.5}
SM2DA(PA4) _{• Fast-mode}
SM3DA(P76) _{• Specified as interval up to time}
1.1
when output state starts changing.
Note 4-6-1: These specifications are theoretical values. Add margin depending on its use.
Specification
typ
max
unit
Tfilt
1/2
tSCL
1/2
1 Tfilt
μs
Tfilt
μs
Tfilt
μs
Tfilt
μs
Continued on next page.
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