LC89057W-VF4A-E Datasheet, PDF (18/59 Pages) Sanyo Semicon Device – Digital Audio Interface Transceiver

LC89057W-VF4A-E
10.1.8 Output clocks block diagram (RMCK, RBCK, RLRCK, SBCK, SLRCK, XMCK)
• _{The relationships between the output clock and switch function are shown below.}
• _{PLL in the figure indicates the PLL source (or TMCK source), and XIN the XIN source.}
• _{The contents in the square brackets [∗∗∗] by the switch function blocks correspond to the write command names.}
• _{The broken lines connecting the switches indicate coordinated switching.}
• _{Lock/Unlock is switched automatically by PLL locking/unlocking.}
• _{Master/Slave is switched by master/slave function switching of demodulation function.}
Master Clock
Generator
XTAL Source
12.288MHz or 24.576MHz
PLL Source
256fs or 512fs
TMCK Source
256fs or 512fs
512fs / 256fs
256fs / 128fs
128fs / 64fs
MUTE
[PRSEL]
12.288MHz / 24.576MHz
6.144MHz / 12.288MHz
3.072MHz / 6.144MHz
MUTE
[XRSEL]
Lock / Unlock
PLL
XIN
PLL 64fs
PLL
12.288MHz
6.144MHz
[XRBCK]
3.072MHz
XIN
MUTE
[OCKSEL] ([SELMTD]=0)
[RCKSEL] ([SELMTD]=1)
RMCK (O)
Master / Slave
RBCK (I/O)
PLL fs
PLL
192kHz
96kHz
48kHz
[XRLRCK]
XIN
MUTE
to internal circuits
128fs
64fs
[PSBCK]
32fs
MUTE
PLL
12.288MHz
6.144MHz
3.072MHz
[XSBCK]
XIN
MUTE
RLRCK (I/O)
[SELMTD]
SBCK (O)
2fs
fs
[PSLRCK]
fs/2
MUTE
PLL
192kHz
96kHz
48kHz
[XSLRCK]
XIN
MUTE
SLRCK (O)
12.288MHz / 24.576MHz
[XMSEL]
6.144MHz / 12.288MHz
XIN
MUTE
XMCK (O)
Figure 10.3 Clock Output Block Diagram
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