K4X56323PG Datasheet, PDF (8/23 Pages) Samsung semiconductor – 8M x32 Mobile-DDR SDRAM

K4X56323PG - 7(8)E/G
Mobile-DDR SDRAM
Extended Mode Register Set(EMRS)
The extended mode register is designed to support partial array self refresh or driver strength control. EMRS cycle is not mandatory
and the EMRS command needs to be issued only when either PASR or DS is used. The default state without EMRS command
issued is half driver strength, and Full array refreshed. The extended mode register is written by asserting low on CS, RAS, CAS,
WE and high on BA1 ,low on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the
extended mode register). The state of address pins A0 ~ A11 in the same cycle as CS, RAS, CAS and WE going low is written in the
extended mode register. Two clock cycles are required to complete the write operation in the extended mode register. Even if the
power-up sequence is finished and some read or write operations is executed afterward, the mode register contents can be changed
with the same command and two clock cycles. But this command must be issued only when all banks are in the idle state. A0 - A2
are used for partial array self refresh and A5 - A6 are used for driver strength control. "High" on BA1 and"Low" on BA0 are used for
EMRS. All the other address pins except A0,A1,A2,A5,A6, BA1, BA0 must be set to low for proper EMRS operation. Refer to the
table for specific codes.
Extended MRS for PASR(Partial Array Self Refresh) &
DS(Driver Strength Control)
BA1 BA0
A11 ~ A10/AP
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ^{Address Bus}
1
0
RFU*
0
0
0
DS
RFU*
PASR
Mode Register
A6 A5
00
01
10
11
DS
Driver Strength
Full
1/2
1/4
1/8
Internal TCSR
Self refresh cycle is controlled
automatically by internal tem-
perature sensor and control cir-
cuit according to the three
temperature ranges ; 45 °C and
85 °C
PASR
A2 A1 A0 Refreshed Area
000
Full Array
0 0 1 1/2 of Full Array
0 1 0 1/4 of Full Array
011
Reserved
100
Reserved
101
Reserved
110
Reserved
111
Reserved
Figure.3 Extended Mode Register Set
Note :
RFU(Reserved for future use) should stay "0" during EMRS cycle
January 2006