K4X56323PG Datasheet, PDF (13/23 Pages) Samsung semiconductor – 8M x32 Mobile-DDR SDRAM

K4X56323PG - 7(8)E/G
Mobile-DDR SDRAM
AC Timming Parameters & Specifications
Parameter
Clock cycle time
Row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Active delay
Last data in to Read command
Col. address to Col. address delay
CL=2
CL=3
Clock high level width
Clock low level width
DQ Output data access time from CK/
CK
DQS Output data access time from
CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS-in high level width
DQS-in low level width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
DQS-in cycle time
Address and Control Input setup time
Address and Control Input hold time
Address & Control input pulse width
DQ & DM setup time to DQS
DQ & DM hold time to DQS
CL=2
CL=3
CL=2
CL=3
CL=2
CL=3
DQ & DM input pulse width
DQ & DQS low-impedence time from CK/CK
DQ & DQS high-impedence time from CK/CK
DQS write postamble time
DQS write preamble time
Symbol
tCK
tRC
tRAS
tRCD
tRP
tRRD
tWR
tDAL
tCDLR
tCCD
DDR266
Min
Max
12.0
7.5
67.5
45
70,000
22.5
22.5
15
15
2tCK+tRP
1
1
tCH
0.45
0.55
tCL
0.45
0.55
2
8
tAC
2
6
2
8
tDQSCK
2
6
tDQSQ
0.6
0.5
1.1
tRPRE
0.9
1.1
tRPST
0.4
0.6
tDQSS
0.75
1.25
tWPRES
0
tWPREH 0.25
tDQSH
0.4
0.6
tDQSL
0.4
0.6
tDSS
0.2
tDSH
0.2
tDSC
0.9
1.1
tIS
1.3
tIH
1.3
tIPW
2.6
tDS
0.8
tDH
0.8
tDIPW
1.8
tLZ
1.0
tHZ
6.0
tWPST
0.4
0.6
tWPRE
0.25
DDR222
Min
Max
15.0
9.0
81
54
70,000
27
27
15
15
2tCK+tRP
1
1
0.45
0.55
0.45
0.55
2.5
8
2.5
6
2.5
8
2.5
6
0.7
0.5
1.1
0.9
1.1
0.4
0.6
0.75
1.25
0
0.25
0.4
0.6
0.4
0.6
0.2
0.2
0.9
1.1
1.5
1.5
3.0
1.1
1.1
2.4
1.0
7.0
0.4
0.6
0.25
Unit Note
ns
ns
ns
ns
ns
ns
ns
-
2
tCK
tCK
tCK
tCK
ns
3
ns
ns
tCK
tCK
tCK
ns
4
tCK
tCK
tCK
tCK
tCK
tCK
ns
1
ns
1
1
ns
5,6
ns
5,6
ns
ns
ns
tCK
tCK
January 2006