K4X56323PG Datasheet, PDF (4/23 Pages) Samsung semiconductor – 8M x32 Mobile-DDR SDRAM

K4X56323PG - 7(8)E/G
Mobile-DDR SDRAM
Input/Output Function Description
SYMBOL
TYPE
DESCRIPTION
CK, CK
Input
Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the
crossing of the positive edge of CK and negative edge of CK. Internal clock signals are derived from
CK/CK.
CKE
Input
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any banks). CKE is
synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input
buffers, excluding CK, CK and CKE , are disabled during power-down and self refresh mode which are
contrived for low standby power consumption.
CS
Input Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder.
All commands are masked when CS is registered HIGH. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the command code.
RAS, CAS, WE Input Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.
DM0,DM1,
DM2,DM3
Input
Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled
HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. DM
pins include dummy loading internally, to match the DQ and DQS loading. For the x32, DM0
corresponds to the data on DQ0-DQ7 ; DM1 corresponds to the data on DQ8-DQ15, DM2 corresponds
to the data on DQ16-DQ23, DM3 corresponds to the data on DQ24-DQ31
BA0, BA1
Input
Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE
command is being applied.
A [n : 0]
Input
Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO
PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the
respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only
one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the
op-code during a MODE REGISTER SET command. BA0 and BA1 determines which mode register
( mode register or extended mode register ) is loaded during the MODE REGISTER SET command.
DQ
I/O
Data Input/Output : Data bus
DQS0,DQS1, I/O
DQS2,DQS3
Data Strobe : Output with read data, input with write data. Edge-aligned with read data, centered in write
data. it is used to fetch write data. For the x32, DQS0 corresponds to the data on DQ0-DQ7 ; DQS1
corresponds to the data on DQ8-DQ15,DQS2 corresponds to the data on DQ16-DQ23, DQS3 corre-
sponds to the data on DQ24-DQ31
NC
-
No Connect : No internal electrical connection is present.
VDDQ
Supply DQ Power Supply : 1.7V to 1.95V
VSSQ
Supply DQ Ground.
VDD
Supply Power Supply : 1.7V to 1.95V
VSS
Supply Ground.
January 2006