K4X51163PE-L Datasheet, PDF (8/20 Pages) Samsung semiconductor – 32Mx16 Mobile DDR SDRAM

K4X51163PE - L(F)E/G
Mobile DDR SDRAM
9.2. Extended Mode Register Set(EMRS)
The extended mode register is designed to support partial array self refresh or driver strength control. EMRS cycle is not mandatory and the
EMRS command needs to be issued only when either PASR or DS is used. The default state without EMRS command issued is half driver
strength, and Full array refreshed. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA1 ,low on
BA0(The Mobile DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The
state of address pins A0 ~ A12 in the same cycle as CS, RAS, CAS and WE going low is written in the extended mode register. Two clock
cycles are required to complete the write operation in the extended mode register. Even if the power-up sequence is finished and some read
or write operations is executed afterward, the mode register contents can be changed with the same command and two clock cycles. But this
command must be issued only when all banks are in the idle state. A0 - A2 are used for partial array self refresh and A5 - A6 are used for
driver strength control. "High" on BA1 and"Low" on BA0 are used for EMRS. All the other address pins except A0,A1,A2,A5,A6, BA1, BA0
must be set to low for proper EMRS operation. Refer to the table for specific codes.
BA1 BA0
A12 ~ A10/AP
Figure 3. Extended Mode Register Set
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ^{Address Bus}
1
0
RFU¹⁾
0
00
DS
RFU¹⁾
PASR
Mode Register
A6 A5
00
01
10
11
DS
Driver Strength
Full
1/2
1/4
1/8
NOTE :
1) RFU(Reserved for future use) should stay "0" during EMRS cycle
PASR
A2 A1 A0 Refreshed Area
000
Full Array
001
1/2 Array
010
1/4 Array
011
Reserved
100
Reserved
101
Reserved
110
Reserved
111
Reserved
- 11 -
June 2007