K4X51163PE-L Datasheet, PDF (13/20 Pages) Samsung semiconductor – 32Mx16 Mobile DDR SDRAM

K4X51163PE - L(F)E/G
Mobile DDR SDRAM
14. AC Timming Parameters & Specifications
Parameter
Clock cycle time
Row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Active delay
Last data in to Read command
CL=2
CL=3
Col. address to Col. address delay
Clock high level width
Clock low level width
DQ Output data access time
from CK/CK
DQS Output data access time
from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS-in high level width
DQS-in low level width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
DQS-in cycle time
Address and Control Input setup time
Address and Control Input hold time
Address & Control input pulse width
DQ & DM setup time to DQS
CL=2
CL=3
CL=2
CL=3
CL=2
CL=3
DQ & DM hold time to DQS
DQ & DM input pulse width
DQ & DQS low-impedence time from CK/CK
DQ & DQS high-impedence time from CK/CK
DQS write postamble time
DQS write preamble time
Refresh interval time
Mode register set cycle time
Power down exit time
Symbol
tCK
tRC
tRAS
tRCD
tRP
tRRD
tWR
tDAL
tCDLR
tCCD
tCH
tCL
tAC
tDQSCK
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tDQSH
tDQSL
tDSS
tDSH
tDSC
tIS
tIH
tIPW
tDS
tDH
tDIPW
tLZ
tHZ
tWPST
tWPRE
tREF
tMRD
tPDEX
DDR333
Min
Max
12.0
6
60
42
70,000
18
18
12
12
2tCK+tRP
1
1
0.45
0.55
0.45
0.55
2
8
2
5.5
2
8
2
5.5
0.5
0.5
1.1
0.9
1.1
0.4
0.6
0.75
1.25
0
0.25
0.4
0.6
0.4
0.6
0.2
0.2
0.9
1.1
1.1
1.1
2.2
0.6
0.6
1.2
1.0
5.5
0.4
0.6
0.25
64
2
1
DDR266
Min
Max
12.0
7.5
67.5
45
70,000
22.5
22.5
15
15
2tCK+tRP
1
1
0.45
0.55
0.45
0.55
2
8
2
6
2
8
2
6
0.6
0.5
1.1
0.9
1.1
0.4
0.6
0.75
1.25
0
0.25
0.4
0.6
0.4
0.6
0.2
0.2
0.9
1.1
1.3
1.3
2.6
0.8
0.8
1.8
1.0
6.0
0.4
0.6
0.25
64
2
1
Unit Note
ns
ns
ns
ns
ns
ns
ns
-
2
tCK
tCK
tCK
tCK
ns
3
ns
ns
tCK
tCK
tCK
ns
4
tCK
tCK
tCK
tCK
tCK
tCK
ns
1
ns
1
1
ns
5,6
ns
5,6
ns
ns
ns
tCK
tCK
ms
tCK
tCK
- 16 -
June 2007