K4X51163PE-L Datasheet, PDF (11/20 Pages) Samsung semiconductor – 32Mx16 Mobile DDR SDRAM

K4X51163PE - L(F)E/G
Mobile DDR SDRAM
12. DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, Tc = -25 to 85°C)
Parameter
Symbol
Test Condition
DDR333 DDR266 Unit Note
Operating Current
(One Bank Active)
IDD0 ^{tRC=tRCmin; tCK=tCKmin; CKE is HIGH; CS is HIGH between valid commands;} 70
address inputs are SWITCHING; data bus inputs are STABLE
65
mA
Precharge Standby Current
in power-down mode
IDD2P
IDD2PS
all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
0.3
mA
0.3
Precharge Standby Current
in non power-down mode
IDD2N ^{all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin;}
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD2NS ^{all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;}
address and control inputs are SWITCHING; data bus inputs are STABLE
15
12
mA
8
8
Active Standby Current
in power-down mode
IDD3P ^{one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin;}
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD3PS ^{one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;}
address and control inputs are SWITCHING; data bus inputs are STABLE
5
mA
2
Active Standby Current
in non power-down mode
(One Bank Active)
IDD3N ^{one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin;}
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD3NS ^{one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;}
address and control inputs are SWITCHING; data bus inputs are STABLE
25
25
mA
20
20
Operating Current
(Burst Mode)
IDD4R ^{one bank active; BL=4; CL=3; tCK = tCKmin; continuous read bursts; I OUT =0 mA}
140
address inputs are SWITCHING; 50% data change each burst transfer
IDD4W ^{one bank active; BL = 4; tCK = tCKmin ; continuous write bursts;}
115
address inputs are SWITCHING; 50% data change each burst transfer
115
mA
100
Refresh Current
Self Refresh Current
tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is HIGH;
IDD5 _{address and control inputs are SWITCHING; data bus inputs are STABLE}
150
CKE is LOW; t CK = t CKmin ;
Extended Mode Register set to all 0’s;
address and control inputs are STABLE;
data bus inputs are STABLE
Internal TCSR
45¹⁾
Full Array 300
-E
1/2 Array
270
IDD6
1/4 Array
255
Full Array 250
-G
1/2 Array
220
135
mA
85
°C
600
500
450
uA
500
400
1/4 Array
205
350
Deep Power Down Current IDD8 Deep Power Down Mode Current
15
uA 2
NOTE :
1) It has +/- 5°C tolerance.
2) DPD(Deep Power Down) function is an optional feature, and it will be enabled upon request.
Please contact Samsung for more information.
3) IDD specifications are tested after the device is properly intialized.
4) Input slew rate is 1V/ns.
5) Definitions for IDD: LOW is defined as V IN ≤ 0.1 * VDDQ ;
HIGH is defined as V IN ≥ 0.9 * VDDQ ;
STABLE is defined as inputs stable at a HIGH or LOW level ;
SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles ;
- data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
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June 2007