K4X51163PE-L Datasheet, PDF (14/20 Pages) Samsung semiconductor – 32Mx16 Mobile DDR SDRAM

K4X51163PE - L(F)E/G
Mobile DDR SDRAM
Parameter
CKE min. pulse width(high and low pulse width)
Auto refresh cycle time
Exit self refresh to active command
Data hold from DQS to earliest DQ edge
Data hold skew factor
Clock half period
Symbol
tCKE
tRFC
tXSR
tQH
tQHS
tHP
DDR333
Min
Max
2
72
120
tHPmin -
tQHS
0.65
tCLmin or
tCHmin
DDR266
Min
Max
2
80
120
tHPmin -
tQHS
0.75
tCLmin or
tCHmin
NOTE :
1) Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
(V/ns)
1.0
0.8
0.6
∆tIS
(ps)
0
+50
+100
This derating table is used to increase t_IS/t_IH in the case where the input slew rate is below 1.0V/ns.
Unit
tCK
ns
ns
ns
ns
ns
∆tIH
(ps)
0
+50
+100
Note
7
2) Minimum 3CLK of tDAL(= tWR + tRP) is required because it need minimum 2CLK for tWR and minimum 1CLK for tRP.
3) tAC(min) value is measured at the high Vdd(1.95V) and cold temperature(-25°C).
tAC(max) value is measured at the low Vdd(1.7V) and hot temperature(85°C).
tAC is measured in the device with half driver strength and under the AC output load condition (Fig.6 in next Page).
4) The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
5) I/O Setup/Hold Slew Rate Derating
I/O Setup/Hold Slew Rate
(V/ns)
1.0
0.8
0.6
∆tIS
(ps)
0
+75
+150
This derating table is used to increase t_DS/t_DH in the case where the I/O slew rate is below 1.0V/ns.
∆tIH
(ps)
0
+75
+150
6) I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Data Rise/Fall Rate
(ns/V)
0
±0.25
±0.5
∆tIS
(ps)
0
+50
+100
∆tIH
(ps)
0
+50
+100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calculated as
1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 1.0V/ns and slew rate 2 =0.8V/ns, then the Delta Rise/Fall Rate =-0.25ns/V.
7) Maximum burst refresh cycle : 8
- 17 -
June 2007