K4H560438E-UC Datasheet, PDF (8/23 Pages) Samsung semiconductor – 256Mb E-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant)

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free
DDR SDRAM
Command Truth Table
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
COMMAND
CKEn-1 CKEn CS
Register
Register
Refresh
Extended MRS
H
Mode Register Set
H
Auto Refresh
H
Entry
Self
Refresh
Exit
L
Bank Active & Row Addr.
H
Read &
Auto Precharge Disable
Column Address _{Auto Precharge Enable}
H
Write &
Auto Precharge Disable
Column Address _{Auto Precharge Enable}
H
Burst Stop
H
Bank Selection
Precharge
H
All Banks
Active Power Down
Entry
H
Exit
L
Entry
H
Precharge Power Down Mode
Exit
L
DM(UDM/LDM for x16 only)
H
No operation (NOP) : Not defined
H
X
L
X
L
H
L
L
L
H
H
X
L
X
L
X
L
X
L
X
L
H
L
L
HX
H
L
L
H
H
L
H
X
L
RAS CAS
L
L
L
L
L
L
H
H
X
X
L
H
H
L
H
L
H
H
L
H
X
X
V
V
X
X
X
X
H
H
X
X
V
V
X
X
X
H
H
WE BA0,1 A10/AP
A0 ~ A9,
A11,A12
L
OP CODE
L
OP CODE
H
X
H
X
H
V
H
V
L
V
L
V
L
X
X
V
X
X
H
X
V
X
H
X
Row Address
L
Column
H
Address
L
Column
H
Address
X
L
X
H
X
X
X
X
Note
1, 2
1, 2
3
3
3
3
4
4
4
4, 6
7
5
8
9
9
Note :1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 1.1 October, 2004