DS_K6F2008U2E Datasheet, PDF (8/10 Pages) Samsung semiconductor – 256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM

K6F2008U2E Family
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
Address
CS1
CS2
WE
Data in
tAS(3)
tWC
tCW(2)
tAW
tWR(4)
tWP(2)
tWP(1)
tDW
tDH
Data Valid
CMOS SRAM
Data out
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2)
applied in case a write ends as CS2 going to low.
DATA RETENTION WAVE FORM
CS1 controlled
VCC
2.7V
tSDR
Data Retention Mode
tRDR
2.2V
VDR
CS1
GND
CS2 controlled
VCC
2.7V
CS2
VDR
0.4V
GND
CS1≥VCC - 0.2V
Data Retention Mode
tSDR
CS2≤0.2V
tRDR
8
Revision 2.0
April 2002