DS_K6F2008U2E Datasheet, PDF (5/10 Pages) Samsung semiconductor – 256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM

K6F2008U2E Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): CL=100pF+1TTL
CL=30pF+1TTL
VTM³⁾
R1²⁾
CL¹⁾
R2³⁾
1. Including scope and jig capacitance
2. R1=3070Ω, R2=3150Ω
3. VTM =2.8V
AC CHARACTERISTICS(Vcc=2.7~3.3V, Industrial product: TA=-40 to 85°C)
Parameter List
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Read Chip Select to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width
Write
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
tRC
tAA
tCO
tOE
tLZ
tOLZ
tHZ
tOHZ
tOH
tWC
tCW
tAS
tAW
tWP
tWR
tWHZ
tDW
tDH
tOW
Speed Bins
55ns¹⁾
Min
Max
70ns
Min
Max
55
-
70
-
-
55
-
70
-
55
-
70
-
25
-
35
10
-
10
-
5
-
5
-
0
20
0
25
0
20
0
25
10
-
10
-
55
-
70
-
45
-
60
-
0
-
0
-
45
-
60
-
40
-
50
-
0
-
0
-
0
20
0
20
25
-
30
-
0
-
0
-
5
-
5
-
1. The parameter is measured with 30pF test load.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
VDR
IDR
tSDR
tRDR
Test Condition
CS1≥Vcc-0.2V¹⁾
Vcc=1.5V, CS1≥Vcc-0.2V¹⁾
See data retention waveform
1. 1) CS1≥Vcc-0.2V, CS2≥Vcc-0.2V(CS1 controlled) or
2) 0≤CS2≤0.2V(CS2 controlled).
2. Typical value are measured at TA=25°C and not 100% tested.
Min
Typ²⁾
Max
Unit
1.5
-
3.3
V
-
0.5
2
µA
0
-
tRC
-
-
ns
-
5
Revision 2.0
April 2002