S5N8943B Datasheet, PDF (7/22 Pages) Samsung semiconductor – G.Lite ADSL Analog Front End IC

2.2 I/O Pins Description
Signal Name Num
Type
RESETN
CS1
CS0
TM1
TM0
48
CMOS
49
CMOS
50
CMOS
51
CMOS
52
CMOS
TX_DATA[13:0]
MCLK
AUXCLK
94~100,
1~7
8
11
CMOS
CMOS
CMOS
TX_DACOP
TX_DACON
COMP_DAC
IREF_DAC
90
Analog
89
Analog
88
Analog
87
Analog
RX_DATA[13:0]
RX_ADCIP
RX_ADCIN
BGR_ADC
REFT_ADC
REFB_ADC
12 ~ 25
28
29
32
33
34
CMOS
Analog
Analog
Analog
Analog
Analog
SCLK
SEN
SDOUT
SDIN
44
CMOS
45
CMOS
46
CMOS
47
CMOS
TX_OUTP
TX_OUTN
TX_FINP
TX_FINN
78
Analog
77
Analog
85
Analog
86
Analog
RX_INP
RX_INN
RX_INPG
RX_INNG
RX_FOUTP
RX_FOUTN
58
Analog
57
Analog
56
Analog
55
Analog
31
Analog
30
Analog
S5N8943B
G.Lite ADSL Analog Front End IC
I/O
Description
General Pins
I System Reset. Active Low
I Chip Select
I Chip Select
I Digital Interface Selection “0” = 14bits , “1”=7bits*2
I “0” = RT , “1” = CO
DAC Interface
I DAC 14bit Data Inputs
If TM1=1, TX_DATA[13:7] is invalid
I Master Clock 4.416MHz(Selectable 8.832M or 17.664M)
I In 7bits Data Interface mode, AUXCLK=MCLK/2
In 14bits Data Interface mode, pin is open or ground.
- DAC Current Positive Output for TX path
- DAC Current Negative Output for TX path
- Compensation Capacitor 0.1uF Connection for TX path
- External Resistor 1.24k Connection
ADC Interface
O ADC 14bit Data Outputs ( If TM1=1, [13:7] is always low)
- ADC Positive Input
- ADC Negative Input
- ADC Band gap Reference Output
- ADC Top Reference Output
- ADC Bottom Reference Output
DSP Interface
I Serial Data Clock
I Serial Data Enable
O Serial Data Output
I Serial Data Input
TX Pass Interface
- Tx Analog Positive Output
- Tx Analog Positive Output
- Tx Filter Analog Positive Input
- Tx Filter Analog Negative Input
RX Pass Interface
- Rx Analog Positive Input
- Rx Analog Negative Input
- Rx Analog External -14dB Gain Positive Input
- Rx Analog External -14dB Gain Negative Input
- Rx Filter Analog Positive Output
- Rx Filter Analog Negative Output
Voltage Reference
CONFIDENTIAL
Preliminary Information (Rev.1.0)
7