S5N8943B Datasheet, PDF (12/22 Pages) Samsung semiconductor – G.Lite ADSL Analog Front End IC

S5N8943B
G.Lite ADSL Analog Front End IC
4.1.1 Register Map
4.1.1.1 Power Control
The power on/off control of AFE blocks on this chip is set by the PWR_CTL register, (XX000), as
described below:
PWR_CTL Register (A4A3A2A1A0=XX000)
DATA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NAME
RESET
VALUE
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
00000000
Power Control is as follow.
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 HEX
DESCRIPCION
0 0 0 0 0 0 0 0 0000 Normal Operation
0 0 0 0 0 0 0 1 0001 N/A
0 0 0 0 0 0 1 0 0002 N/A
0 0 0 0 0 1 0 0 0004 TX DAC Power Down
0 0 0 0 1 0 0 0 0008 TX Filter & AGC Power Down
0 0 0 1 0 0 0 0 0010 RX ADC Power Down
0 0 1 0 0 0 0 0 0020 Rx Filter Power Down
0 1 0 0 0 0 0 0 0040 Rx AGC Power Down
1 0 0 0 0 0 0 0 0080 VCXO DAC Power Down
Adding Power Down (based on upper power down)
0 0 0 0 0 0 1 1 0003 N/A
0 0 0 0 1 1 0 0 000C TX Path Power Down
0 1 1 1 0 0 0 0 0070 Rx Path Power Down
1 1 1 1 1 1 1 1 00FF Whole Chip Power Down
CONFIDENTIAL
Preliminary Information (Rev.1.0)
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