S5N8943B Datasheet, PDF (18/22 Pages) Samsung semiconductor – G.Lite ADSL Analog Front End IC

S5N8943B
G.Lite ADSL Analog Front End IC
4.2 Data Interface
4.2.1 Physical Interface
l ADC and DAC data transmission between S5N8943B01 and S5N8944
l Parallel Interface(S5N8944) : 29 pin (14 ADC bit data, 14 DAC bit data, MCLK)
l Parallel Interface
: 16 pin ( 7 ADC bit data, 7 DAC bit data, MCLK,AUXCLK)
S5N8944
(DMT)
TX_DATA[13:0]
MCLK
AUXCLK
RX_DATA[13:0]
S5N8943B01
(AFE)
4.2.2 Waveform
MCLK
T_CYC
T_D
T_PWH
T_PWL
T_D
TX_DATA
TX_DATA[13:0] TX_DATA[13:0] TX_DATA[13:0] TX_DATA[13:0]
T_SU
T_H
RX_DATA
RX_DATA[13:0]
RX_DATA[13:0]
Figure 4.2.1 Waveform of 14bit parallel interface (TM1=0)
MCLK
T_SU2
T_D
T_H2
AUXCLK
TX_DATA
N-1
TX_DATA[6:0]
N-1
TX_DATA[13:7]
N
TX_DATA[6:0]
N
TX_DATA13:7]
RX_DATA
N-1
RX_DATA[6:0]
N-1
RX_DATA[13:7]
N
RX_DATA[6:0]
N
RX_DATA[13:7]
Figure 4.2.2 Waveform of 7bit parallel interface (TM1=1)
Parameter
Symbol Min
Typ
Max Unit
Note
MCLK Clock Period
T_CYC
226
nS MCLK=4.416MHz
MCLK High Time
T_PWH
113
nS MCLK=4.416MHz
MCLK Low Time
T_PWL
113
nS MCLK=4.416MHz
DATA Delay after MCLK
T_D
10
nS
RX_DATA setup to MCLK
T_SU
30
nS MCLK=4.416MHz
RX_DATA hold to MCLK
T_H
84
nS MCLK=4.416MHz
AUXCLK setup to MCLK
T_SU2
10
nS
AUXCLK hold to MCLK
T_H2
10
nS
CONFIDENTIAL
Preliminary Information (Rev.1.0)
18