S5N8943B Datasheet, PDF (16/22 Pages) Samsung semiconductor – G.Lite ADSL Analog Front End IC

S5N8943B
G.Lite ADSL Analog Front End IC
4.1.1.5 Clock Selection
Main functions of Clock Selection are frequency selection of each MCLK/AUXCLK/ADC. The individual
bit definitions are given below.
CLK_SEL Register (A4A3A2A1A0=XX100)
DATA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NAME
RESET
VALUE
CK1 CK0
00
TM1, CK[1:0] : Clock Selection has eight possible clocking configuration as follow.
TM1 2 Phase CK1 CK0 HEX
MCLK
AUXCLK
DAC
0
OFF
0
0 0000 4.416 MHz
0
4.416 MHz
0
OFF
0
1 0001 4.416 MHz
0
4.416 MHz
0
OFF
1
0 0002 8.832MHz
0
8.832MHz
0
OFF
1
1 0003 8.832MHz
0
8.832MHz
1
ON
0
0 0000 8.832MHz 4.416 MHz 4.416 MHz
1
ON
0
1 0001 8.832MHz 4.416 MHz 4.416 MHz
1
ON
1
0 0002 17.664MHz 8.832MHz 8.832MHz
1
ON
1
1 0003 17.664MHz 8.832MHz 8.832MHz
ADC
2.208 MHz
4.416 MHz
4.416 MHz
8.832MHz
4.416 MHz
2.204 MHz
8.832 MHz
4.416 MHz
CONFIDENTIAL
Preliminary Information (Rev.1.0)
16