K4H560438J Datasheet, PDF (4/24 Pages) Samsung semiconductor – 256Mb J-die DDR SDRAM Specification

K4H560438J
K4H560838J
K4H561638J
1.0 Key Features
• V_DD : 2.5V ± 0.2V, V_DDQ : 2.5V ± 0.2V for DDR266, 333
• V_DD : 2.6V ± 0.1V, V_DDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II Lead-Free & Halogen-Free package
• RoHS compliant
DDR SDRAM
2.0 Ordering Information
Part No.
Org.
Max Freq.
Interface
K4H560438J-LC/LB3
K4H560438J-LC/LB0
64M x 4
B3(DDR333@CL=2.5)
B0(DDR266@CL=2.5)
SSTL2
K4H560838J-LC/LCC
K4H560838J-LC/LB3
32M x 8
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
SSTL2
K4H561638J-LC/LCC
K4H561638J-LC/LB3
16M x 16
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
SSTL2
Note
1. "-B3"(DDR333, CL=2.5) can support "-B0"(DDR266, CL=2.5)/ "-A2"(DDR266, CL=2).
2. “L” of Part number(12th digit) stands for RoHS compliant and Halogen-Free product.
Package
66pin TSOP II
Lead-Free & Halogen-Free
66pin TSOP II
Lead-Free & Halogen-Free
66pin TSOP II
Lead-Free & Halogen-Free
Note
1, 2
2
2
1, 2
2
1, 2
3.0 Operating Frequencies
Speed @CL2
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
CC(DDR400@CL=3)
-
166MHz
200MHz
3-3-3
B3(DDR333@CL=2.5)
133MHz
166MHz
-
2.5-3-3
A2(DDR266@CL=2.0)
133MHz
133MHz
-
2-3-3
B0(DDR266@CL=2.5)
100MHz
133MHz
-
2.5-3-3
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Rev. 1.12 August 2008