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K4H560438J Datasheet, PDF (10/24 Pages) Samsung semiconductor – 256Mb J-die DDR SDRAM Specification
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K4H560438J
K4H560838J
K4H561638J
DDR SDRAM
16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks Double Data Rate SDRAM
9.0 General Description
The K4H560438J / K4H560838J / K4H561638J is 268,435,456 bits of double data rate synchronous DRAM organized as 4x 16,777,216
/ 4x 8,388,608 / 4x 4,194,304 words by 4/8/16bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous fea-
tures with Data Strobe allow extremely high performance up to 400Mb/s per pin. I/O transactions are possible on both edges of DQS.
Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of
high performance memory system applications.
10.0 Absolute Maximum Rating
Parameter
Voltage on any pin relative to VSS
Voltage on VDD & VDDQ supply relative to VSS
Storage temperature
Power dissipation
Short circuit current
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
PD
IOS
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
1.5
50
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Unit
V
V
°C
W
mA
11.0 DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Symbol
Min
Max
Unit Note
Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333)
VDD
2.3
2.7
V
Supply voltage(for device with a nominal VDD of 2.6V for DDR400)
VDD
2.5
2.7
V
I/O Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333)
VDDQ
2.3
2.7
V
I/O Supply voltage(for device with a nominal VDD of 2.5V for DDR400)
VDDQ
2.5
2.7
V
I/O Reference voltage
VREF
0.49*VDDQ 0.51*VDDQ
V
1
I/O Termination voltage(system)
VTT
VREF-0.04 VREF+0.04
V
2
Input logic high voltage
VIH(DC) VREF+0.15 VDDQ+0.3
V
Input logic low voltage
VIL(DC)
-0.3
VREF-0.15
V
Input Voltage Level, CK and CK inputs
VIN(DC)
-0.3
VDDQ+0.3
V
Input Differential Voltage, CK and CK inputs
VID(DC)
0.36
VDDQ+0.6
V
3
V-I Matching: Pullup to Pulldown Current Ratio
VI(Ratio)
0.71
1.4
-
4
Input leakage current
II
-2
2
uA
Output leakage current
IOZ
-5
5
uA
Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V
IOH
-16.8
mA
Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V
IOL
16.8
mA
Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V
IOH
-9
mA
Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V
IOL
9
mA
Note :
1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may not
exceed +/-2% of the dc value.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track vari-
ations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range,
for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers
due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to
source voltages from 0.1 to 1.0.
10 of 24
Rev. 1.12 August 2008
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