K4H560438J Datasheet, PDF (16/24 Pages) Samsung semiconductor – 256Mb J-die DDR SDRAM Specification

K4H560438J
K4H560838J
K4H561638J
DDR SDRAM
19.0 AC Timming Parameters & Specifications
Parameter
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
CL=2.0
Clock cycle time
CL=2.5
CL=3.0
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup
Symbol
tRC
tRFC
tRAS
tRCD
tRP
tRRD
tWR
tWTR
tCK
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tDSS
tDSH
tDQSH
tDQSL
tIS
tIH
tIS
CC
(DDR400@CL=3.0)
Min
Max
55
70
40
70K
15
15
10
15
2
-
-
6
12
5
10
0.45 0.55
0.45 0.55
-0.55 +0.55
-0.65 +0.65
-
0.4
0.9
1.1
0.4
0.6
0.72 1.28
0
0.25
0.2
0.2
0.35
0.35
0.6
0.6
0.7
B3
(DDR333@CL=2.5)
Min
Max
60
72
42
70K
18
18
12
15
1
7.5
12
6
12
-
-
0.45 0.55
0.45 0.55
-0.6
+0.6
-0.7
+0.7
-
0.45
0.9
1.1
0.4
0.6
0.75 1.25
0
0.25
0.2
0.2
0.35
0.35
0.75
0.75
0.8
A2
(DDR266@CL=2.0)
Min
Max
65
75
45
70K
20
20
15
15
1
7.5
12
7.5
12
-
-
0.45 0.55
0.45 0.55
-0.75 +0.75
-0.75 +0.75
-
0.5
0.9
1.1
0.4
0.6
0.75 1.25
0
0.25
0.2
0.2
0.35
0.35
0.9
0.9
1.0
B0
(DDR266@CL=2.5) _Unit
Min
Max
Note
65
ns
75
ns
45
70K ns
20
ns
20
ns
15
ns
15
ns
1
tCK
10
12 ns
7.5
12 ns
-
-
0.45 0.55 tCK
0.45 0.55 tCK
-0.75 +0.75 ns
-0.75 +0.75 ns
-
0.5 ns 22
0.9
1.1 tCK
0.4
0.6 tCK
0.75 1.25 tCK
0
ns 13
0.25
tCK
0.2
tCK
0.2
tCK
0.35
tCK
0.35
tCK
0.9
ns 15, 17~19
0.9
ns 15, 17~19
1.0
ns 16~19
Address and Control Input hold time(slow) tIH
0.7
0.8
Data-out high impedence time from CK/CK tHZ
-0.65 +0.65 -0.7
Data-out low impedence time from CK/CK tLZ
-0.65 +0.65 -0.7
Mode register set cycle time
tMRD
10
12
DQ & DM setup time to DQS
tDS
0.4
0.45
DQ & DM hold time to DQS
tDH
0.4
0.45
+0.7
+0.7
1.0
-0.75
-0.75
15
0.5
0.5
+0.75
+0.75
1.0
-0.75
-0.75
15
0.5
0.5
ns 16~19
+0.75 ns 11
+0.75 ns 11
ns
ns j, k
ns _{j, k}
Control & Address input pulse width
DQ & DM input pulse width
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
Output DQS valid window
Clock half period
Data hold skew factor
DQS write postamble time
Active to Read with Auto precharge
command
Autoprecharge write recovery +
Precharge time
Power Down Exit Time
tIPW
2.2
2.2
2.2
2.2
ns 18
tDIPW 1.75
1.75
1.75
1.75
ns 18
tXSNR 75
75
75
75
ns
tXSRD 200
200
200
200
tCK
tREFI
7.8
7.8
7.8
7.8
tHP
tQH
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
tCLmin
tHP _{or tCHmin}
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
us 14
ns 21
ns 20, 21
tQHS
0.5
0.55
0.75
0.75 ns 21
tWPST 0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6 tCK 12
tRAP
15
18
20
20
tDAL
tPDEX
(tWR/tCK)
+
(tRP/tCK)
1
(tWR/tCK)
+
(tRP/tCK)
1
(tWR/tCK)
+
(tRP/tCK)
1
(tWR/tCK)
+
(tRP/tCK)
1
tCK 23
tCK
16 of 24
Rev. 1.12 August 2008