S3C2400 Datasheet, PDF (398/488 Pages) Samsung semiconductor – RISC MICROPROCESSOR

S3C2400 RISC MICROPROCESSOR
IIC-BUS INTERFACE
START
Master Rx mode has been
configured.
Write slave address to
IICDS
Write 0xB0(M/R Start) to
IICSTAT
The data of the IICDS(slave
address) is transmitted
ACK period and then
interrupt is pending
Stop?
Y
N
Read a new data from
IICDS
Clear pending bit to
resume
SDA is shifted to IICDS
Write 0x90(M/R Stop) to
IICSTAT
Clear Pending bit
Wait until the stop
condition takes effect.
END
Figure 20-7. Operations for Master/Receiver Mode
20-8