S3C2400 Datasheet, PDF (316/488 Pages) Samsung semiconductor – RISC MICROPROCESSOR

S3C2400 RISC MICROPROCESSOR
INTERRUPT CONTROLLER
INTERRUPT PENDING REGISTER (INTPND)
Each of the 32 bits in the interrupt pending register shows whether the corresponding interrupt request is the highest
priority one that is unmasked and waits for the interrupt to be serviced. Since INTPND is located after the priority
logic, only one bit can be set to 1 at most, and that is the very interrupt request generating IRQ to CPU. In interrupt
service routine for IRQ, you can read this register to determine the interrupt source to be serviced among 32 sources.
Like the SRCPND, this register has to be cleared in the interrupt service routine after clearing SRCPND register. We
can clear a specific bit of INTPND register by writing a data to this register. It clears only the bit positions of INTPND
corresponding to those set to one in the data. The bit positions corresponding to those that are set to 0 in the data
remains as they are with no change.
Register
INTPND
Address
0X14400010
R/W
Description
R/W Indicates the interrupt request status.
0 = The interrupt has not been requested
1 = The interrupt source has asserted the interrupt
request
Reset Value
0x00000000
NOTE: If the FIQ mode interrupt is occurred, the corresponding bit of INTPND will not be turned on. Because the INTPND
register is available only for IRQ mode interrupt.
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