S3C2400 Datasheet, PDF (282/488 Pages) Samsung semiconductor – RISC MICROPROCESSOR

S3C2400 RISC MICROPROCESSOR
UART
UART TRANSMIT BUFFER REGISTER(HOLDING REGISTER & FIFO REGISTER)
UTXHn has an 8-bit data for transmission data
Register
UTXH0
UTXH1
Address
0x15000020(L)
0x15000023(B)
0x15004020(L)
0x15004023(B)
R/W
Description
W UART channel 0 transmit buffer register
(by byte)
W UART channel 1 transmit buffer register
(by byte)
Reset Value
–
–
UTXHn
TXDATAn
Bit
[7:0] Transmit data for UARTn
NOTE: (L): When the endian mode is Little endian.
(B): When the endian mode is Big endian.
Description
UART RECEIVE BUFFER REGISTER (HOLDING REGISTER & FIFO REGISTER)
URXHn has an 8-bit data for received data
Register
URXH0
URXH1
Address
0x15000024(L)
0x15000027(B)
0x15004024(L)
0x15004027(B)
R/W
Description
R UART channel 0 receive buffer register
(by byte)
R UART channel 1 receive buffer register
(by byte)
Initial State
–
Reset Value
–
–
URXHn
RXDATAn
Bit
[7:0] Receive data for UARTn
Description
Initial State
–
NOTE: When an overrun error occurs, the URXHn must be read. If not, the next received data will also make an overrun
error, even though the overrun bit of USTATn had been cleared.
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