K4D28163HD Datasheet, PDF (3/16 Pages) Samsung semiconductor – 128Mbit DDR SDRAM

K4D28163HD
128M DDR SDRAM
2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
FEATURES
• 3.3V + 5% power supply for device operation
• 2.5V + 5% power supply for I/O interface
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 3 (clock)
-. Burst length (2, 4 and 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive
going edge of the system clock
• Differential clock input
• No Wrtie-Interrupted by Read Function
• 2 DQS’s ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 32ms refresh period (4K cycle) for -36/-40
• 64ms refresh period (4K cycle) for -50/-60
• 66pin TSOP-II
• Maximum clock frequency up to 275MHz
• Maximum data rate up to 550Mbps/pin
ORDERING INFORMATION
Part NO.
K4D28163HD-TC36
K4D28163HD-TC40
K4D28163HD-TC50
K4D28163HD-TC60
Max Freq.
275MHz
250MHz
200MHz
166MHz
Max Data Rate
550Mbps/pin
500Mbps/pin
400Mbps/pin
333Mbps/pin
Interface
SSTL_2
Package
66pin TSOP-II
GENERAL DESCRIPTION
FOR 2M x 16Bit x 4 Bank DDR SDRAM
The K4D28163HD is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2.097,152 words
by 16 bits, fabricated with SAMSUNG ’s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 1.1GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
-3-
Rev. 1.4(Aug. 2002)