K4D28163HD Datasheet, PDF (13/16 Pages) Samsung semiconductor – 128Mbit DDR SDRAM

K4D28163HD
AC CHARACTERISTICS
128M DDR SDRAM
Parameter
Sym-
bol
CK cycle time
CL=3 tCK
CK high level width
tCH
CK low level width
tCL
DQS out access time from CK tDQSCK
Output access time from CK tAC
Data strobe edge to Dout edge tDQSQ
Read preamble
Read postamble
tRPRE
tR P S T
CK to valid DQS-in
DQS-In setup time
tDQSS
tWPRES
DQS-in hold time
tWPREH
DQS write postamble
DQS-In high level width
tWPST
tDQSH
DQS-In low level width
tDQSL
Address and Control input setup tIS
Address and Control input hold tI H
DQ and DM setup time to DQS tDS
DQ and DM hold time to DQS tDH
Clock half period
tHP
Data output hold time from DQS tQ H
-36
Min
Max
3.6
6
0.45
0.55
0.45
0.55
-0.6
0.6
-0.6
0.6
-
0.4
0.9
1.1
0.4
0.6
0.85
1.15
0
-
0.35
-
0.4
0.6
0.4
0.6
0.4
0.6
0.9
-
0.9
-
0.4
-
0.4
-
tCLmin
or
-
tCHmin
tHP-0.4
-
-40
Min
Max
4.0
7
0.45
0.55
0.45
0.55
-0.6
0.6
-0.6
0.6
-
0.4
0.9
1.1
0.4
0.6
0.85
1.15
0
-
0.35
-
0.4
0.6
0.4
0.6
0.4
0.6
0.9
-
0.9
-
0.4
-
0.4
-
tCLmin
or
-
tCHmin
tHP-0.4
-
-50
Min
Max
5.0
10
0.45
0.55
0.45
0.55
-0.7
0.7
-0.7
0.7
-
0.45
0.9
1.1
0.4
0.6
0.8
1.2
0
-
0.3
-
0.4
0.6
0.4
0.6
0.4
0.6
1.0
-
1.0
-
0.45
-
0.45
-
tCLmin
or
-
tCHmin
tHP-0.45
-
-60
Min
6.0
0.45
0.45
-0.75
-0.75
-
0.9
0.4
0.75
0
0.25
0.4
0.4
0.4
1.1
1.1
0.5
0.5
tCLmin
or
tCHmin
tHP-0.5
Max
10
0.55
0.55
0.75
0.75
0.5
1.1
0.6
1.25
-
-
0.6
0.6
0.6
-
-
-
-
-
-
Unit Note
ns
tCK
tCK
ns
ns
ns 1
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns 1
ns 1
Note 1 :
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst
case
output vaild window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
- 13 -
Rev. 1.4(Aug. 2002)