K4T1G084QD Datasheet, PDF (22/27 Pages) Samsung semiconductor – 1Gb D-die DDR2 SDRAM Specification

K4T1G084QD
K4T1G164QD
DDR2 SDRAM
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode
bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode
dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential
mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guar-
anteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be
tied externally to VSS through a 20 ohm to 10 K ohm resisor to insure proper operation.
DQS/
DQS
DQ
DM
DQS
t_DQSH
t_DQSL
DQS
t_WPRE
VIH(ac)
D
VIL(ac)
t_DS
DMin
D
V_IH(ac) ^tDS
DMin
VIL(ac)
VIH(dc)
D
VIL(dc)
t_DH
DMin
<Data input (write) timing>
t_WPST
D
t_DH
V_IH(dc)
DMin
V_IL(dc)
t_CH
t_CL
CK
CK/CK
CK
DQS/DQS
DQ
DQS
DQS
t_RPRE
t_DQSQmax
Q
t_QH
t_RPST
Q
Q
Q
t_DQSQmax
t_QH
<Data output (read) timing>
5. AC timings are for linear signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester
correlation.
7. All voltages are referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operation are guaranteed for the full voltage range specified.
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Rev. 1.0 March 2007