K4T1G084QD Datasheet, PDF (14/27 Pages) Samsung semiconductor – 1Gb D-die DDR2 SDRAM Specification

K4T1G084QD
K4T1G164QD
DDR2 SDRAM
9.0 OCD default characteristics
Description
Output impedance
Output impedance step size for OCD calibration
Pull-up and pull-down mismatch
Output slew rate
Parameter
Sout
Min
Nom
Max
Normal 18ohms
See full strength default driver characteristics
0
1.5
0
4
1.5
5
Unit
ohms
ohms
ohms
V/ns
Notes
1,2
6
1,2,3
1,4,5,6,7,8
Note :
1. Absolute Specifications (0°C ≤ T_CASE ≤ +95°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)
2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/Ioh must be less than 23.4 ohms for
values of VOUT between VDDQ and VDDQ- 280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV;
VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV.
3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.
4. Slew rate measured from V_IL(AC) to V_IH(AC).
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is
guaranteed by design and characterization.
6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the DRAM uncertainty.
Output slew rate load :
VTT
25 ohms
Output
(VOUT)
Reference
Point
7. DRAM output slew rate specification applies to 400Mb/sec/pin, 533Mb/sec/pin, 667Mb/sec/pin and 800Mb/sec/pin speed bins.
8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification.
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Rev. 1.0 March 2007