S3C72P9 Datasheet, PDF (155/225 Pages) Samsung semiconductor – SINGLE-CHIP MICROCONTROLLER HAS BEEN DESIGNED FOR HIGH PERFORMANCE USING

S3C72P9/P72P9 (Preliminary Spec)
TIMERS and TIMER/COUNTERS
TC0 MODE REGISTER (TMOD0)
TMOD0 is the 8-bit mode control register for timer/counter 0. It is addressable by 8-bit write instructions. One bit,
TMOD0.3, is also 1-bit writeable. RESET clears all TMOD0 bits to logic zero and disables TC0 operations.
F90H
F91H
TMOD0.3 TMOD0.2
"0"
"0"
"0"
TMOD0.6 TMOD0.5 TMOD0.4
TMOD0.2 is the enable/disable bit for timer/counter 0. When TMOD0.3 is set to "1", the contents of TCNT0,
IRQT0, and TOL0 are cleared, counting starts from 00H, and TMOD0.3 is automatically reset to "0" for normal
TC0 operation. When TC0 operation stops (TMOD0.2 = "0"), the contents of the TC0 counter register TCNT0 are
retained until TC0 is re-enabled.
The TMOD0.6, TMOD0.5, and TMOD0.4 bit settings are used together to select the TC0 clock source. This
selection involves two variables:
— Synchronization of timer/counter operations with either the rising edge or the falling edge of the clock signal
input at the TCL0 pin, and
— Selection of one of four frequencies, based on division of the incoming system clock frequency, for use in
internal TC0 operation.
Bit Name
TMOD0.7
TMOD0.6
TMOD0.5
TMOD0.4
TMOD0.3
TMOD0.2
TMOD0.1
TMOD0.0
Table 11-6. TC0 Mode Register (TMOD0) Organization
Setting
0
0,1
Resulting TC0 Function
Always logic zero
Specify input clock edge and internal frequency
1
Clear TCNT0, IRQT0, and TOL0 and resume counting
immediately (This bit is automatically cleared to logic zero
immediately after counting resumes.)
0
Disable timer/counter 0; retain TCNT0 contents
1
Enable timer/counter 0
0
Always logic zero
0
Always logic zero
Address
F91H
F90H
11-17