S3C72P9 Datasheet, PDF (131/225 Pages) Samsung semiconductor – SINGLE-CHIP MICROCONTROLLER HAS BEEN DESIGNED FOR HIGH PERFORMANCE USING

I/O PORTS
S3C72P9/P72P9 (Preliminary Spec)
Table 10-1. I/O Port Overview
Port
I/O
Pins Pin Names
Address
Function Description
0
I/O
4
P0.0–P0.3
FF0H
4-bit I/O port.
1-bit and 4-bit read/write and test is possible.
Individual pins are software configurable as
input or output.
Individual pins are software configurable as
open-drain or push-pull output.
4-bit pull-up resistors are software assignable;
pull-up resistors are automatically disabled for
output pins.
1
I
4
P1.0–P1.3
FF1H
4-bit input port.
1-bit and 4-bit read and test is possible.
4-bit pull-up resistors are assignable.
2
I/O
3
P2.0–P2.2
FF2H
Same as port 0 except that port 2 is 3-bit I/O
port.
3
I/O
4
P3.0–P3.3
FF3H
Same as port 0.
4, 5
I/O
8
P4.0–P4.3
P5.0–P5.3
FF4H
FF5H
4-bit I/O ports.
1-, 4-bit or 8-bit read/write and test is possible.
Individual pins are software configurable as
input or output.
4-bit pull-up resistors are software assignable;
pull-up resistors are automatically disabled for
output pins.
6, 7
I/O
8
P6.0–P6.3
P7.0–P7.3
FF6H
FF7H
Same as P4 and P5.
8, 9
I/O
8
P8.0–P8.3
P9.0–P9.3
FF8H
FF9H
Same as P4 and P5.
Table 10-2. Port Pin Status During Instruction Execution
Instruction Type
1-bit test
1-bit input
4-bit input
8-bit input
1-bit output
4-bit output
8-bit output
Example
BTST
LDB
LD
LD
P0.1
C,P1.3
A,P7
EA,P4
BITR P2.3
LD P2,A
LD P6,EA
Input Mode Status
Input or test data at each pin
Output latch contents undefined
Transfer accumulator data to the
output latch
Output Mode Status
Input or test data at output latch
Output pin status is modified
Transfer accumulator data to the
output pin
10-2