DS_K7B803625B Datasheet, PDF (10/19 Pages) Samsung semiconductor – 256Kx36 & 512Kx18-Bit Synchronous Burst SRAM

K7B803625B
K7B801825B
Output Load(A)
Dout
Zo=50Ω
256Kx36 & 512Kx18 Synchronous SRAM
RL=50Ω
30pF*
VL=1.5V for 3.3V I/O
VDDQ/2 for 2.5V I/O
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
Dout
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
319Ω / 1667Ω
353Ω / 1538Ω
5pF*
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
PARAMETER
SYMBOL
-65
MIN MAX
-75
MIN MAX
UNIT
Cycle Time
Clock Access Time
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
tCYC
tCD
tOE
tLZC
tOH
tLZOE
tHZOE
7.5
-
8.5
-
ns
-
6.5
-
7.5
ns
-
3.5
-
3.5
ns
2.5
-
2.5
-
ns
2.5
-
2.5
-
ns
0
-
0
-
ns
-
3.5
-
3.5
ns
Clock High to Output High-Z
Clock High Pulse Width
Clock Low Pulse Width
Address Setup to Clock High
Address Status Setup to Clock High
Data Setup to Clock High
Write Setup to Clock High (GW, BW, WEX)
tHZC
-
3.8
-
4.0
ns
tCH
2.2
-
2.5
-
ns
tCL
2.2
-
2.5
-
ns
tAS
1.5
-
2.0
-
ns
tSS
1.5
-
2.0
-
ns
tDS
1.5
-
2.0
-
ns
tWS
1.5
-
2.0
-
ns
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
Address Status Hold from Clock High
Data Hold from Clock High
Write Hold from Clock High (GW, BW, WEX)
Address Advance Hold from Clock High
tADVS
tCSS
tAH
tSH
tDH
tWH
tADVH
1.5
-
2.0
-
ns
1.5
-
2.0
-
ns
0.5
-
0.5
-
ns
0.5
-
0.5
-
ns
0.5
-
0.5
-
ns
0.5
-
0.5
-
ns
0.5
-
0.5
-
ns
Chip Select Hold from Clock High
ZZ High to Power Down
ZZ Low to Power Up
tCSH
tPDS
tPUS
0.5
-
0.5
-
ns
2
-
2
-
cycle
2
-
2
-
cycle
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
2. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS
is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
3. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
4. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
- 10 -
Nov. 2003
Rev 3.0