BU6569GVW Datasheet, PDF (6/17 Pages) Rohm – Camera Image Processor with ADPCM / MIDI / MP3 / AAC / HE-AAC Audio

BU6569GVW
Technical Note
●Terminal functions
PIN Land
No.
No.
PIN Name
1
A1 GND
2
C3 D8
3
B2 D7
4
B1 D6
5
C2 D5
6
D3 D4
7
D2 VDD
8
D1 D3
9
E3 D2
10
E2 D1
11
E1 D0
12
E5 ADVB
13
E4 CSB
14
F2 WRB
15
F1 RDB
16
F5 INT
17
F4 RESETB
18
F3 LED0
19
G1 VIB0
20
G2 DIGLR
21
G3 DIGCK
22
G4 DACMCK
23
H1 _DIGDIN
24
H3 DIGDOUT
25
J1 FSYNC
26
J2 PCMDIN
27
H4 DCLK
28
H2 VDDIO1
29
K1 L_OUT
30
G5 R_OUT
31
L1 AVSS
32
L2 AVDD
33
K3 AVSS
34
H5 VREF
35
K2 MONO_OUT
36
J3 VDDIO3
37
K4 USB_DM
38
L3 USB_DP
39
F6 USB_RDY
40
G6 GND
41
J4 VDDIO2
42
L4 SD_CLK
43
K5 SD_CMD
44
H6 VDD
45
J5 SD_DAT0
46
L5 FL_CEB
47
K6 FL_RB
48
F7 LCDCS1B
49
G7 LCDCS2B
50
L6
LCDWRB
/ FL_WEB
51
H7
LCDRDB
/ FL_REB
52
K7
LCDA0
/ FL_ALE
53
J6 TEST
54
L7
LCDD0
/ FL_D0
LCDD1
55
F8 / FL_D1
/ SD_DAT1
In/Out
/Analog
-
In/Out
In/Out
In/Out
In/Out
In/Out
-
In/Out
In/Out
In/Out
In/Out
In
In
In
In
Out
In
Out
Out
In/Out
In/Out
In/Out
In
Out
In/Out
In
In/Out
-
Analog
Analog
-
-
-
Analog
Analog
-
Analog
Analog
In/Out
-
-
Out
In/Out
-
In/Out
Out
In
Out
Out
Out
Out
Out
In
In/Out
In/Out
Active
Level
GND
DATA
DATA
DATA
DATA
DATA
PWR
DATA
DATA
DATA
DATA
Low
Low
Low
Low
*
Low
-
-
-
CLK
CLK
DATA
DATA
-
DATA
CLK
PWR
DATA
DATA
GND
PWR
GND
-
DATA
PWR
-
-
-
GND
PWR
CLK
DATA
PWR
DATA
Low
Low
Low
Low
Low
Low
*
Low
DATA
DATA
Init
-
In *1
In *1
In *1
In *1
In *1
-
In *1
In *1
In *1
In *1
-
-
-
-
Low
-
Low
Low
In
In
Out/Low
-
-
In
-
In
-
-
-
-
-
-
-
-
-
In
In
Out/Low
-
-
-
Out/Low
-
Out/Low
-
-
-
High
-
-
-
-
Out/Low
Out/Low
Function explanation
Power
source
system
Digital ground
-
Host data bus: bit 8
1
Host data bus: bit 7
1
Host data bus: bit 6
1
Host data bus: bit 5
1
Host data bus: bit 4
1
CORE power supply
-
Host data bus: bit 3
1
Host data bus: bit 2
1
Host data bus: bit 1
1
Host data bus: bit 0
1
Address latch enable
1
Chip select signal
1
Write enable signal
1
Read enable signal
1
Interrupt signal
1
System reset signal
1
LED control signal
1
Vibrator control signal
1
Sampling clock for audio data
1
Bit clock for audio data (64Fs/32Fs)
1
Master clock for audio data(256Fs/384Fs)
1
Audio data input
1
Audio data output
1
Sampling clock for PCM data
1
PCM data input
1
Bit clock for PCM data
1
Digital I/O power supply (System 1)
1
Stereo L-channel analog output *12, *13
A
Stereo R-channel analog output *12, *13
A
Analog ground
A
Analog power supply
A
Analog ground
A
AC (signal) GND
Be sure to connect a 1-μF bypass capacitor A
between VREF and AVSS.
Monaural analog output *13, *14
A
USB power supply (System 3)
3
UBS D- pin
3
USB D+ pin
3
I/O port for USB intialization
3
Digital ground
-
Digital I/O power supply (System 2)
2
SD card clock output
2
SD card command input/output
2
Core power supply
-
SD card data: bit0
2
NAND Flash chip enable
2
NAND Flash Ready/Busy
2
LCD controller chip select signal 1
2
LCD controller chip select signal 2
2
LCD controller write enable signal
/ NAND Flash write enable signal
2
LCD controller read enable signal
/ NAND Flash read enable signal
2
LCD controller command parameter identification
signal/ NAND Flash address latch enable signal
2
Test mode terminal (Connect to GND.)
2
LCD controller data bus: bit 0
/ NAND Flash data bus: bit 0
2
LCD controller data bus: bit 1
/ NAND Flash data bus: bit 1
2
/ SD card IF bus: bit 1
Function
division
-
HOST
HOST
HOST
HOST
HOST
-
HOST
HOST
HOST
HOST
HOST
HOST
HOST
HOST
HOST
SYS
SYS
SYS
AUD
AUD
AUD
AUD
AUD
AUD
AUD
AUD
-
AUD
AUD
-
-
-
AUD
AUD
-
USB
USB
USB
-
-
SD
SD
-
SD
FL
FL
LCD
LCD
LCD
/ FL
LCD
/ FL
LCD
/ FL
SYS
LCD
/ FL
LCD
/ FL
/ SD
I/O type
-
D*2
D*2
D*2
D*2
D*2
-
D*2
D*2
D*2
D*2
G
G*3
G
G
C
B
D*4
D*4
D*5
D*5
D*5
D*6
D*7
D*5
D*6
D*5
-
I
I
-
-
-
J
I
-
H
H
D*3
-
-
C
D*3
-
D*3
D*4
G*3
D*7
D*7
D*7
D*7
D*7
A
D*3
D*3
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6/16
2009.07 - Rev.A