BU6569GVW Datasheet, PDF (5/17 Pages) Rohm – Camera Image Processor with ADPCM / MIDI / MP3 / AAC / HE-AAC Audio

BU6569GVW
Technical Note
●Block Diagram
SDC/MMC
Interface
NAND Flash
Interface
SD
Card/MMC
I/F
NAND Flash
I/F
Audio
sequencer for
AutoPlay
FIFO
2KB
FIFO
1KB
Audio Processor
MIDI engine
Audio
path
switch
Out sync
VIB0
LED0
DAC
IIS I/F
Audio Interface
HOST Interface
FIFO
1KB
HOST I/F
Register Array
ADPCM Codec
LCD controller I/F
PCM I/F
LCD control
display data
2-line type serial
for Camera, TV-
Encoder
YUV=4:2:2
RGB=5:6:5
2-line serial
control
Brightness compenent
D range change
YUV=4:2:2
YUV=4:4:4
1/n resizing
cropping
Camera
Interface
Max UXGA
(1600×1200)
multistep zoom
Image processing
(filter processing)
JPEG
Codec
YUV=4:2:2
Clock control
Power down control
internal clock
XIN1,XOUT1
XIN2,XOUT2
RESETB
PLL
(2 channels)
RGB ⇔ YUV
color space conversion
TV Encoderr I/F
Memory
I/F
LCD display frame memory
160KB
Viewing Buffer memory
64KB
Expanded overlay memory
32KB
Mask memory
10KB
Multi step zoom memory
4KB
MIDI engine work memory
Audio Processor work memory
Audio Processor
Sequence Date/
MIDI Wave Data
192KB
Play List
16KB
General purpose
Input/output
USB FS I/F
from each blocks Interrupt controller
USB Interface
TV Encoder
Interface
CAMRST
Interrupt to
HOST
●Recommended Application Circuit
Camera
TV-Encoder
USB Host
AFE
TE_PIXCLK
TE_VSYNC
TE_HSYNC
TED[7:0]
USB_DP
USB_DM
LCDCS1B
LCDA0
LCDWRB
LCDRDB
LCDD[15:0]
LCDD[16]
LCDD[17]
LCDCS2B
BU6569GVW
PCMDIN
FSYNC
DCLK
DIGLR
DIGCK
DIGDIN
DIGDOUT
SD_CLK
SD_CMD
SD_DAT0
FL_CEB
FL_RB
Main LCD
Sub LCD
LCDD[3:1]
SDC/MMC
NAND
Flash
Host CPU
※Data is prepared separately about each register setup. Please refer to the Development Scheme on page 14.
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© 2009 ROHM Co., Ltd. All rights reserved.
5/16
2009.07 - Rev.A