BU6569GVW Datasheet, PDF (10/17 Pages) Rohm – Camera Image Processor with ADPCM / MIDI / MP3 / AAC / HE-AAC Audio

BU6569GVW
● Terminal Layout
Technical Note
31
AVSS
32
AVDD
38
USB_DP
42
SD_CLK
46
FL_CEB
50
LCDWRB
54
LCDD0
57
LCDD3
60
LCDD6
61
LCDD7
62
GND
29
L_OUT
35
MONO_OUT
33
AVSS
37
USB_DM
43
SD_CMD
47
FL_RB
52
LCDA0
58
LCDD4
64
LCDD9
65
LCDD10
66
LCDD11
25
FSYNC
26
PCMDIN
36
VDDIO3
41
45
53
59
67
68
70
69
SD_DAT0
TEST
LCDD5
LCDD12
LCDD13
LCDD15
LCDD14
23
28
24
27
DIGDIN
VDDIO1
DIGDOUT
34
VREF
44
VDD
51
LCDRDB
63
LCDD8
71
LCDD16
72
LCDD17
73
VDDIO2
19
VIB0
20
DIGLR
21
DIGCK
22
30
40
49
56
79
R_OUT
GND
LCDCS2B
LCDD2
CAMVS
76
SDC
74
CAMRST
15
14
18
17
RDB
WRB
LED0
16
39
48
55
80
77
75
INT
USB_RDY LCDCS1B
LCDD1
CAMHS
CAMCKI
SDA
11
10
9
D0
D1
D2
8
7
6
D3
VDD
D4
5
2
D5
D8
13
12
110
101
88
87
82
78
ADVB
VSS4
TED6
CAMD6
CAMD5
CAMD0
CAMCKO
119
115
109
102
96
92
84
81
D14
XOUT2
TED7
TE_D1
TE_VSYNC
CAMD2
VDD
118
114
108
103
97
93
85
83
D15
XIN2
GND
TED2
TE_HSYNC
CAMD3
CAMD1
4
3
D6
D7
1
120
GND
D9
1
2
113
117
112
106
105
99
94
89
86
A1
A2
XOUT1
XIN1
TED4
TE_PIXCLK
CAMD7
CAMD4
116
111
107
104
100
98
95
91
90
D13
PLL_FILTER VDDIO4
TED5
TED3
TED0
VDDIO2
GND
3
4
5
6
7
8
9
10
11
（Bottom View）
●Timing Chart
1. HOST interface timing
1.1 System timing
Symbol
tXIN
Table 1.1 BU6569GVW timing conditions (system)
Details
MIN. TYP. MAX. Unit
BU6569GVW Clock input cycle
38.5
-
372.0 ns
Conditions
tXIN2
BU6569GVW Clock input cycle 2
33.3
-
100.0 ns
DutyXIN
BU6569GVW clock duty
45.0
50.0 55.0
% "H" width / cycle
tSCLK
BU6569GVW SCLK clock cycle
19.2
-
-
ns
DutySCLK
BU6569GVW SCLK clock duty
33.3
50.0 66.6
% "H" width / cycle
tCAMCKO
Camera clock output cycle
19.2
-
-
ns
DutyCAMCKO
Camera clock output duty
33.3
50.0 66.6
% "H" width / cycle
tCAMCKI
Camera clock input cycle
19.2
-
-
ns
DutyCAMCKI
Camera clock input duty
45.0
50.0 55.0
% "H" width / cycle
tRESETB
RESETB "L" pulse width
＊Regulation all at threshold of VDDIO1/2
1.0
-
-
μs
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© 2009 ROHM Co., Ltd. All rights reserved.
10/16
2009.07 - Rev.A