BU6569GVW Datasheet, PDF (13/17 Pages) Rohm – Camera Image Processor with ADPCM / MIDI / MP3 / AAC / HE-AAC Audio

BU6569GVW
4. LCD transfer timing
Transfer timing to LCD is shown below.
LCDCSB1
LCDA0
LCDWRB
LCDD0-17
2
WH+1 WH+1
WL+1 WL+1
COMMAND transfer
WH+1 WH+1
WH+2
WL+1 WL+1 WL+1
DATA transfer
Technical Note
Without COMMAND transfer,
this portion will be skipped.
(WH and WL can be set from 0 to 15.)
Figure 4-1 MAIN LCD data transfer waveform（Unit：tSCLK）
5. Digital input interface timing
5.1. IIS input timing
The input timing in IIS I/F is shown below.
DIGLR
DIGDIN
DIGCK
tIISS tIISH
Symbol
Details
tIISS
IIS input data setup time
MIN. TYP. MAX. Unit
5
-
-
ns
tIISH
IIS input data hold time
5
-
-
ns
＊Regulation all at threshold of VDDIO11/2
5.2. PCM input timing
The input timing in PCM I/F is shown below.
FSYNC
PCMDIN
DCLK
(DCLK Polarity='0')
DCLK
(DCLK Polarity='1')
tPCMS tPCMH
Symbol
Details
tPCMS PCM data setup time
MIN. TYP. MAX. Unit
5
-
-
ns
tPCMH PCM data hold time
5
-
-
ns
＊Regulation all at threshold of VDDIO11/2
6. SD Card I/F / MMC I/F input / output timing (Host to/from SD Card)
【SD Card I/F / MMC I/F output】
tTRlh
tTRhl
【SD Card I/F / MMC I/F input】
SDCLK
SDCMD
SDDAT0-3
tODcmd
tODdat
SDCLK
SDCMD
SDDAT0-3
tSUcmd tHDcmd
tSUdat tHDdat
Table 1.6-1 BU6569GVW timing conditions（SD Card I/F / MMC I/F output）
Symbol
Details
MIN. TYP. MAX. Unit
tTRlh
SDCLK clock rise time
-
-
5(＊) ns
Table 1.6-2 BU6569GVW timing conditions（SD Card I/F / MMC I/F input）
Symbol
Details
MIN. TYP. MAX. Unit
tSUcmd SDCMD setup time
7
-
-
ns
tTRhl
SDCLK clock fall time
-
-
5(＊) ns
tHDcmd SDCMD hold time
1
-
tODcmd
SDCMD output delay
against SDCLK falling
-2
(＊)
-
2 (＊) ns
tSUdat SDDAT0-3 setup time
10
-
tODdat
SDDAT0-3 output delay
against SDCLK falling
-2
(＊)
-
7 (＊) ns
tHDdat SDDAT0-3 hold time
1
-
(＊)At no load condition
＊Regulation all at threshold of VDDIO21/2
＊Regulation all at threshold of VDDIO21/2
-
ns
-
ns
-
ns
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13/16
2009.07 - Rev.A