BU26154MUV_15 Datasheet, PDF (57/90 Pages) Rohm – Monaural Audio CODEC with Touch Panel Interface

BU26154MUV
Datasheet
FMTO
This bit sets the transmission mode.
Setting
Explanation
0
LRCLK transfer mode
1
Frame synchronization transfer mode
PCMFO24
This bit sets PCM format of the SAI transmission.
Setting
Explanation
0x2
16bit PCM
0x3
24bit PCM
Other than the
above
This is prohibited from setting
SAI Receiver Control Register
MAPCON
0x0
INDEX
R
W
0x62 0x63
b07
b06
(Initial)
PCMFI24
1
1
b05
FMTI
0
b04
MSBI
0
b03
ISSCKI
0
b02
AFOI
0
b01
DLYI
0
b00
WSLI
0
This register is a register controlling SAI reception format setting, and RECPLAY bit of the Record/Playback Running
Control register, please change this register in recording stop state (0x0), and please use it by setting again same as the
SAI transmission side (SAI Transmitter Control register).
WSLI
This bit selects LRCLK polarity of the LSI. This bit must be set to “1” when at Flame synchronous transfer mode (FMTI is “1”).
Setting
Explanation
0
Left channel is received when SAI_LRCLK is “L” level, right
channel is received at SAI_LRCLK is “H” level.
1
Left channel is received when SAI_LRCLK is “H” level, right
channel is received at SAI_LRCLK is “L” level.
DLYI
This bit specifies the existence for serial input data one clock delay of master device.
Setting
Explanation
0
Serial data delay existence
1
Serial data delay nothing
AFOI
This bit sets the receiving data to be Left-justify or Right-justify. This bit must be set to “0” when at Flame synchronous
transfer mode (FMTI is “1”).
Setting
Explanation
0
Left-justify
1
Right-justify
ISSCKI
This bit sets the sampling frequency of SAI_BCLK pin.
Setting
Explanation
0
32fs
1
64fs
MSBI
This bit sets the SAI receiving data to be MSB-first or LSB-first.
Setting
Explanation
0
MSB first
1
LSB first
FMTI
This bit sets the receiving mode
Setting
Explanation
0
LRCLK transfer mode
1
Frame synchronization transfer mode
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26.Oct.2015 Rev.002