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BU26154MUV_15 Datasheet, PDF (46/90 Pages) Rohm – Monaural Audio CODEC with Touch Panel Interface
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BU26154MUV
Datasheet
Clock Input / Output Control Register
MAPCON
INDEX
b07
b06
b05
b04
b03
b02
b01
b00
R
W
(Initial)
0x0
0x0e 0x0f
-
-
-
PLLISEL
CLKSEL
-
-
-
0
0
0
0
0
This register is to select internal clock. It is to use or not use and to create MCLKI input or internal clock divided PLL.
CLKSEL[2:0]
Choose a clock to be use
Setting
Explanation
0x0
Using PLL lets you output 256fs clock from PLL.
The PLL output is just used inside this LSI.
0x2
Using PLL lets you output 512fs clock from PLL.
The clock that is divided by 1/2 the PLL output is used inside this LSI.
0x3
Using PLL lets you output 1024fs clock from PLL
The clock that is divided by 1/4 the PLL output is used inside this LSI.
0x4
Input 256fs clock to MCLKI terminal and PLL is not used.
MCLKI terminal input is just used in this LSI.
0x6
Input 512fs clock to MCLKI terminal and PLL is not used.
The clock that is divided by ½ the MCLKI terminal input is used inside this LSI.
0x7
Input 1024fs clock than MCLKI terminal and use it without using PLL.
The clock that is divided by 1/4 the MCLKI terminal input is used inside this LSI.
PLLISEL[1:0]
When this bit chooses to input clock into PLL and does not use PLL, please set register to 0x0.
Setting
Explanation
0x0
Prohibited from setting
0x1
Use MCLKI terminal input
0x2
Use BCLK terminal input
Software Reset Register
MAPCON
INDEX
b07
b06
b05
b04
b03
b02
b01
b00
R
W
(Initial)
0x0
0x10 0x11
-
-
-
-
-
-
-
SOFTRST
-
-
-
-
-
-
-
0
This register is for software reset. CPU interface and this register are reset by writing SOFTRST bit to “1”. And then, write
“0” for releasing reset.
Record/Playback Running Control Register
MAPCON
INDEX
b07
b06
b05
b04
b03
b02
b01
b00
R
W
(Initial)
0x0
0x12 0x13
-
-
-
-
-
RECPLAY
-
-
-
-
-
0
0
0
This register controls start / stop of the recording/playback operation of the LSI.
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TSZ02201-0V2V0E500110-1-2
26.Oct.2015 Rev.002
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