BU26154MUV_15 Datasheet, PDF (16/90 Pages) Rohm – Monaural Audio CODEC with Touch Panel Interface

BU26154MUV
Datasheet
Function Description
Clock Control
Main modules that make sound path of the LSI inside operate with 1024fs Audio Clock.
Audio Clock can be selected whether divided clock of 256fs/512fs/1024fs from MCLKI or generated clock from Audio PLL.
When PLL is used, PLL generates internal clock. The input clock into PLL can be selected from either MCLKI port or
SAI_BCLK port by setting Clock Input / Output Control register. PLL generates 256fs clock of sampling frequency.
The registers about Audio Clock setting: Sampling Rate Setting Register, FPLLM, FPLLNL, FPLLNH, FPLLD, FPLLFL,
FPLLFH, FPLLFDL, FPLLFDH, Clock Input / Output Control register, Clock Input Select Register
・The sequence of PLL setting
1. Stop PLL output by setting PLLOE bit to “0”.
2. Disable PLL by setting PLLEN bit to “0”.
3. Set PFLLM, FPPNL, FPLLNH, FPLLD, FPLLFL, FPLLFH, FPLLFDL, FPLLFDH.
4. Set input port by PLLISEL bit.
5. Set PLLEN bit to “1”.
6. Wait for the PLL stabilizing time as the table “PLL Stabilizing Time”.
7. Set PLLOE bit to “1”.
8. Start recording or playback.
PLL Stabilizing Time
PLL stability time
10msec
- Related Register
Sampling Rate Setting Register
PLLNL, PLLNH Register
PLLML, PLLMH Register
PLLDIV Register
Clock Enable Register
Clock Input / Output Control Register
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26.Oct.2015 Rev.002