BU26154MUV_15 Datasheet, PDF (56/90 Pages) Rohm – Monaural Audio CODEC with Touch Panel Interface

BU26154MUV
Datasheet
SEMODE [7]/SEMODEB [7]
You choose a course putting Filter Block, and please refer to the clause of "the signal flow" of "the function explanation" for
Filter Block.
SEMODE[7]/
Explanation
SEMODEB [7]
0
Use Filter Block on Recording path.
1
Use Filter Block on Playback path.
SEMODE [2:0]/ SEMODEB [2:0]
This sets distribution of EQ/Notch Filter.
SEMODE[2:0]/
SEMODEB[2:0]
0x0
Notch5 band / EQ0 band
0x1
Notch4 band / EQ1 band
0x2
Notch3 band / EQ2 band
0x3
Notch2 band / EQ3 band
0x4
Notch1 band / EQ4 band
0x5
Notch0 band / EQ5 band
Explanation
When "0x01" is set, Band0 to Band3 filters Notch, and Band4 becomes the EQ.
SAI Transmitter Control Register
MAPCON
0x0
INDEX
R
W
0x60 0x61
b07
b06
(Initial)
PCMFO24
1
1
b05
FMTO
0
b04
b03
b02
MSBO
0
ISSCKO
0
AFOO
0
b01
DLYO
0
b00
WSLO
0
This register controls the SAI transmission format setting. The RECPLAY bit of the Record/Playback Running Control
register, please change this register in recording stop state (0x0), and please use it by setting again same as the SAI
reception side (SAI Receiver Control register).
WSLO
You appoint LRCLK polarity at the time of the transmission of this LSI, and please set this bit in "1" in (FMTO at the time of
"1") in a transfer mode by all means in the frame same period.
Setting
Explanation
0
Left channel transmission at SAI_LRCLK is “L” level; right
channel transmission at SAI_LRCLK is “H” level.
1
Left channel transmission at SAI_LRCLK is “H” level; right
channel transmission at SAI_LRCLK is “L” level.l
DLYO
This bit appoints 1 clock delay existence / nothing of transmission data.
Setting
Explanation
0
Serial data delay existence
1
Serial data delay nothing
AFOO
You appoint in front of filling / attacking the enemy from behind of transmission data, and, in the case of a slave mode, this
bit is ignored, and it is in previous final stage is fixed, and please set this bit in "0" in (FMTO at the time of "1") in a transfer
mode by all means in the frame same period.
Setting
Explanation
0
Left-justify
1
Right-justify
ISSCKO
This bit sets BCLK terminal to 32fs/64fs.
Setting
0
32fs
1
64fs
Explanation
MSBO
This bit sets the MSB first /LSB first data transmission.
Setting
Explanation
0
MSB first
1
LSB first
www.rohm.com
© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
56/86
TSZ02201-0V2V0E500110-1-2
26.Oct.2015 Rev.002