H8S-2643 Datasheet, PDF (981/1277 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 24 Power-Down Modes
driven high, a transition is made to the program execution state via the reset exception handling
state.
24.7.2 Hardware Standby Mode Timing
Figure 24.4 shows an example of hardware standby mode timing.
When the STBY pin is driven low after the RES pin has been driven low, a transition is made to
hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high,
waiting for the oscillation stabilization time, then changing the RES pin from low to high.
Oscillator
RES
STBY
Oscillation
stabilization
time
Reset
exception
handling
Figure 24.4 Hardware Standby Mode Timing
24.8 Watch Mode
24.8.1 Watch Mode
CPU operation makes a transition to watch mode when the SLEEP instruction is executed in high-
speed mode or sub-active mode with SBYCR SSBY = 1, LPWRCR DTON = 0, and TCSR
(WDT1) PSS = 1.
In watch mode, the CPU is stopped and supporting modules other than WDT1 are also stopped.
The contents of the CPU’s internal registers, the data in internal RAM, and the statuses of the
internal supporting modules (excluding the SCI, ADC, and 14-bit PWM) and I/O ports are
retained.
Rev. 3.00 Jan 11, 2005 page 927 of 1220
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