H8S-2643 Datasheet, PDF (16/1277 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Item
10.8.2 Register
Configuration
Page
386
10.10.2 Register 393
Configuration
394
395
10.11.1 Overview 398
Revisions (See Manual for Details)
(1) Port 8 Data Direction Register (P8DDR)
Description amended
... and in software standby mode. DMAC is initialized by a
manual reset, so the pin states are determined by the
specification of P8DDR and P8DR.
(1) Port A Data Direction Register (PADDR)
Description amended
… PADDR is initialized to H'00 by a power-on reset, and in
hardware standby mode. … when a transition is made to
software standby mode. See section 24.2.1, Standby Control
Register (SBYCR), for details.
• Modes 4 to 6
… irrespective of the value of PADDR. When pins are not used
as address outputs, …
(2) Port A Data Register (PADR)
Description amended
… PADR is initialized to H'00 by a power-on reset, and in
hardware standby mode. …
(4) Port A MOS Pill-Up Control Register (PAPCR)
Description amended
…In modes 4 to 6, if a pin is in the input state in accordance
with the settings in PFCR, and in DDR, setting the
corresponding PAPCR bit to 1 turns on the MOS input pill-up for
than pin.
In mode 7, if a pin is in the input state in accordance with the
settings in DDR, setting the corresponding PAPCR bit to 1 turns
on the MOS input pill-up for than pin.
PAPCR is initialized by a manual reset or to H'00 by a power-on
reset, and in hardware standby mode. …
(5) Port A Open Drain Control Register (PAODR)
Description amended
… PAODR is initialized to H'00 by a power-on reset, and in
hardware standby mode. …
Description amended
Port B is n 8-bit I/O port. Port B pins also function as address
bus outputs; ...
Rev. 3.00 Jan 11, 2005 page xvi of liv