H8S-2643 Datasheet, PDF (316/1277 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 8 DMA Controller
Figure 8.7 illustrates operation in repeat mode.
Address T
Transfer
1 byte or word transfer performed in
response to 1 transfer request
IOAR
Address B
Legend:
Address T = L
Address B = L + (–1)^DTID · (2^DTSZ · (N–1))
Where : L = Value set in MAR
N = Value set in ETCR
Figure 8.7 Operation in Repeat mode
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts. External requests can be set for channel B only.
Rev. 3.00 Jan 11, 2005 page 262 of 1220
REJ09B0186-0300O