H8S2199R Datasheet, PDF (902/1222 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Section 29 On-Screen Display (OSD)
29.6.4 4fsc/2fsc
For a 4fsc/2fsc signal, either an external clock signal is input, or a crystal oscillator can be
connected. If an external clock signal is input, the signal must be amplified using a dedicated
amplifier circuit; this is set using the register.
Either 4fsc or 2fsc input can be selected.
If a 2fsc signal is input, some colors cannot be displayed. For details, see table 29.7.
29.6.5 OSDV Interrupts
Interrupts triggered by the Vsync signal input to the OSD (OSDV interrupts) can be generated. In
superimposed mode, interrupts are triggered by the external Vsync signal, and in text display
mode, they are triggered by the internal Vsync signal generated in the sync separator.
29.6.6 OSD Format Register (DFORM)
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
15
TVM2
0
R/W
7
—
1
—
14
TVM1
0
R/W
6
—
1
—
13
TMV0
0
R/W
5
—
1
—
12
11
10
9
8
FSCIN FSCEXT —
OSDVE OSDVF
0
0
0
0
0
R/W
R/W
—
R/W R/(W)*
4
3
2
1
0
—
—
DTMV LDREQ VACS
1
1
0
0
0
—
—
R/W
R/W R/(W)*
Note: * Only 0 can be written to clear the flag.
The DFORM is used to set the TV format and control display data RAM.
The DFORM is a 16-bit read/write register. When reset, it is initialized to H'00F8. Bits other than
bits 12, 11, and 7 to 3 are cleared to 0 in module stop, sleep, standby, watch, subactive, and
subsleep modes.
When the module stop bit of the sync separator is 0, bits 12 and 11 must not be rewritten.
Rev.2.00 Jan. 15, 2007 page 858 of 1174
REJ09B0329-0200