H8S2199R Datasheet, PDF (686/1222 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Section 26 Servo Circuits
read is invalid. If a read is attempted, an undetermined value is read out. It is initialized to H'7FFF
by a reset, or in stand-by or module-stop mode.
CFG Lock LOWER Data Register (CFRLDR)
Bit : 15
14
13
12
11
10
9
8
CFRLDR15 CFRLDR14 CFRLDR13 CFRLDR12 CFRLDR11 CFRLDR10 CFRLDR9 CFRLDR8
Initial value :
1
0
0
0
0
0
0
0
R/W : W
W
W
W
W
W
W
W
Bit :
7
6
5
4
3
2
1
0
CFRLDR7 CFRLDR6 CFRLDR5 CFRLDR4 CFRLDR3 CFRLDR2 CFRLDR1 CFRLDR0
Initial value :
0
0
0
0
0
0
0
0
R/W : W
W
W
W
W
W
W
W
CFRLDR is a 16-bit write-only register used to set the lock range on the LOWER side when
capstan speed lock is detected, and to set the limit value on LOWER side when limiter function is
in use.
When lock is being detected, if the drum speed is detected within the lock range, the lock counter
that has been set by CFRCS 1 and 0 bits of CFVCR register decrements the count. If the set value
of CFRCS 1 and 0 matches the number of times of occurrence of locking, the computation of the
digital filter in the drum phase system can be controlled automatically. Also, if the CFG speed
error data is under the CFRLDR value when the limiter function is in use, the CFRLDR value can
be used as the data for computation by the digital filter.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. No
read is valid. If a read is attempted, an undetermined value is read out. It is initialized to H'8000 by
a reset, or in stand-by or module-stop mode.
Capstan Speed Error Detection Control Register (CFVCR)
Bit :
Initial value :
R/W :
7
CFCS1
0
R/W
6
CFCS0
0
R/W
5
CFOVF
0
R/(W)^*1
4
3
2
CFRFON CF-R/UNR CPCNT
0
0
0
R/W
R
R/W
1
CFRCS1
0
(R)^*2/W
0
CFRCS0
0
(R)^*2/W
Notes: 1. Only 0 can be written.
2. If read-accessed, the counter value is read out.
CFVCR is an 8-bit read/write register that controls the operation of capstan speed error detection.
Bit 3 accepts only read, and bit 5 accepts only read and 0 write. It is initialized to H'00 by a reset,
or in stand-by or module-stop mode.
Rev.2.00 Jan. 15, 2007 page 642 of 1174
REJ09B0329-0200