H8S2199R Datasheet, PDF (1133/1222 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

H'D139: Timer Counter J TCJ: Timer J
Appendix B Internal I/O Registers
Bit :
Initial value :
R/W :
7
TDR17
1
R
6
TDR16
1
R
5
TDR15
1
R
4
TDR14
1
R
3
TDR13
1
R
2
TDR12
1
R
1
TDR11
1
R
0
TDR10
1
R
H'D13A: Timer Mode Register J TMJ: Timer J
Bit
:
Initial value :
R/W
:
7
PS11
0
R/W
6
PS10
0
R/W
5
ST
0
R/W
4
3
2
1
0
8/16
PS21 PS20
TGL
T/R
0
0
0
0
0
R/W
R/W
R/W
R
R/W
Timer output/remote-controller output
select bit
0
TMJ-1 timer output
(Initial value)
1
TMJ-1 toggle output (data
transmitted from remote
controller)
TMJ-2 toggle flag
0
TMJ-2 toggle output is 0 (Initial value)
1
TMJ-2 toggle output is 1
TMJ-2 input clock select bits
PS21
PS20
Description
0
0
PSS, count at φ/16384
(Initial value)
1
PSS, count at φ/2048
1
0
Count at TMJ-1 underflow
1
Count at rising/falling edge of external clock (IRQ2)*
Note: * External clock edge selection is set in the IRQ edge select register (IEGR).
See section 6.2.4, IRQ Edge Select Register (IEGR).
8-bit/16-bit operation select bit
0
TMJ-1 and TMJ-2 operate separately (Initial value)
1
TMJ-1 and TMJ-2 operate together as 16-bit
Remote-controlled operation start bit
0
Stop TMJ-1 clock supply in remote control mode
1
Start TMJ-1 clock supply in remote control mode
(Initial value)
TMJ-1 input clock select bits
PS11
PS10
Description
0
0
PSS, count at φ/512
(Initial value)
1
PSS, count at φ/256
1
0
PSS, count at φ/4
1
Count at rising/falling edge of external clock (IRQ1)*
Note: * External clock edge selection is set in the IRQ edge select register (IEGR).
See section 6.2.4, IRQ Edge Select Register (IEGR).
When using external clock in remote control mode, set opposite edges for IRQ1 and IRQ2 edges
(eg. When falling edge is set for IRQ1, set rising edge for IRQ2. When rising edge is set for IRQ1,
set falling edge for IRQ2).
Rev.2.00 Jan. 15, 2007 page 1089 of 1174
REJ09B0329-0200