H8S2199R Datasheet, PDF (1102/1222 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Appendix B Internal I/O Registers
H'D0B8: Servo Interrupt Enable Register 1 SIENR1: Servo Interrupt
Bit
:
Initial value :
R/W
:
7
IEDRM3
0
R/W
6
IEDRM2
0
R/W
5
IEDRM1
0
R/W
4
IECAP3
0
R/W
3
IECAP2
0
R/W
2
IECAP1
0
R/W
1
IEHSW2
0
R/W
0
IEHSW1
0
R/W
HSW timing generator (OVW, match, STRIG)
interrupt enable bit
0 Interrupt request is disabled by IRRHSW1
(Initial value)
1 Interrupt request is enabled by IRRHSW1
HSW timing generation (counter clear, capture)
interrupt enable bit
0 Interrupt request is disabled by IRRHSW2 (Initial value)
1 Interrupt request is enabled by IRRHSW2
Capstan speed error detection (OVF, latch)
interrupt enable bit
0 Interrupt request is disabled by IRRCAP1 (Initial value)
1 Interrupt request is enabled by IRRCAP1
Capstan speed error detection (lock detection)
interrupt enable bit
0 Interrupt request is disabled by IRRCAP2 (Initial value)
1 Interrupt request is enabled by IRRCAP2
Capstan phase error detection interrupt enable bit
0 Interrupt request is disabled by IRRCAP3 (Initial value)
1 Interrupt request is enabled by IRRCAP3
Drum speed error detection (OVF, latch)
interrupt enable bit
0 Interrupt request is disabled by IRRDRM1 (Initial value)
1 Interrupt request is enabled by IRRDRM1
Drum speed error detection (lock detection)
interrupt enable bit
0 Interrupt request is disabled by IRRDRM2 (Initial value)
1 Interrupt request is enabled by IRRDRM2
Drum phase error detection interrupt enable bit
0 Interrupt request is disabled by IRRDRM3
(Initial value)
1 Interrupt request is enabled by IRRDRM3
Rev.2.00 Jan. 15, 2007 page 1058 of 1174
REJ09B0329-0200