H8S2199R Datasheet, PDF (310/1222 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Section 13 Timer J
13.2.3 Timer J Status Register (TMJS)
Bit :
7
6
5
4
3
2
1
0
TMJ2I TMJ1I
—
—
—
—
—
—
Initial value :
0
0
1
1
1
1
1
1
R/W : ^{R/(W)* R/(W)*}
—
—
—
—
—
—
Note: * Only 0 can be written to clear the flag.
The timer J status register (TMJS) works to indicate issuance of the interrupt request of timer J.
The TMJS is an 8-bit read/write register. When reset, the TMJS is initialized to H'3F.
Bit 7⎯TMJ2I Interrupt Requesting Flag (TMJ2I): This is the TMJ2I interrupt requesting flag.
This flag is set out when the TMJ-2 underflows.
Bit 7
TMJ2I
0
1
Description
[Clearing condition]
When 0 is written after reading 1
[Setting condition]
When the TMJ-2 underflows
(Initial value)
Bit 6⎯TMJ1I Interrupt Requesting Flag (TMJ1I): This is the TMJ1I interrupt requesting flag.
This flag is set out when the TMJ-1 underflows.
TMJ1I interrupt requests will also be made under a 16-bit operation.
Bit 6
TMJ1I
0
1
Description
[Clearing condition]
When 0 is written after reading 1
[Setting condition]
When the TMJ-1 underflows
(Initial value)
Bits 5 to 0⎯Reserved: These bits cannot be modified and are always read as 1.
Rev.2.00 Jan. 15, 2007 page 266 of 1174
REJ09B0329-0200