PD46184182B_15 Datasheet, PDF (9/34 Pages) Renesas Technology Corp – 18M-BIT DDR II SRAM 2-WORD BURST OPERATION

μPD46184182B, μPD46184362B
Burst Sequence
Linear Burst Sequence Table
A0
A0
External Address
0
1
1st Internal Burst Address
1
0
Truth Table
Operation
LD# R, W# CLK
WRITE cycle
L L L→H
Load address, input write data on
consecutive K and K# rising edge
READ cycle
L H L→H
Load address, read data on
consecutive C and C# rising edge
NOP (No operation)
H × L→H
Clock stop
× × Stopped
DQ
Data in
Input data
Input clock
Data out
Output data
Output clock
High-Z
Previous state
D(A1)
K(t+1) ↑
Q(A1)
C#(t+1) ↑
D(A2)
K#(t+1) ↑
Q(A2)
C(t+2) ↑
Remarks 1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges
except if C and C# are HIGH then Data outputs are delivered at K and K# rising edges.
3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of
K. All control inputs are registered during the rising edge of K.
4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. A1 refers to the address input during a WRITE or READ cycle. A2 refers to the next internal burst
address in accordance with the linear burst sequence.
7. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most
rapid restart by overcoming transmission line charging symmetrically.
R10DS0114EJ0200 Rev.2.00
Nov 09, 2012
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