PD46184182B_15 Datasheet, PDF (5/34 Pages) Renesas Technology Corp – 18M-BIT DDR II SRAM 2-WORD BURST OPERATION

μPD46184182B, μPD46184362B
Pin Description
Symbol
A0
A
DQ0 to
DQxx
LD#
R, W#
BWx#
K, K#
C, C#
Type
Input
Input/Outpu
t
Input
Input
Input
Input
Input
(1/2)
Description
Synchronous Address Inputs: These inputs are registered and must meet the setup and
hold times around the rising edge of K. All transactions operate on a burst of two words
(one clock period of bus activity). A0 is used as the lowest order address bit permitting a
random starting address within the burst operation on x18 and x36 devices. These inputs
are ignored when device is deselected, i.e., NOP (LD# = HIGH).
Synchronous Data IOs: Input data must meet setup and hold times around the rising
edges of K and K#. Output data is synchronized to the respective C and C# data clocks
or to K and K# if C and C# are tied to HIGH.
x18 device uses DQ0 to DQ17.
x36 device uses DQ0 to DQ35.
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be
defined. This definition includes address and read/write direction. All transactions operate
on a burst of 2 data (one clock period of bus activity).
Synchronous Read/Write Input: When LD# is LOW, this input designates the access type
(READ when R, W# is HIGH, WRITE when R, W# is LOW) for the loaded address. R, W#
must meet the setup and hold times around the rising edge of K.
Synchronous Byte Writes: When LOW these inputs cause their respective byte to be
registered and written during WRITE cycles. These signals must meet setup and hold
times around the rising edges of K and K# for each of the two rising edges comprising the
WRITE cycle. See Pin Arrangement for signal to data relationships.
x18 device uses BW0#, BW1#.
x36 device uses BW0# to BW3#.
See Byte Write Operation for relation between BWx# and Dxx.
Input Clock: This input clock pair registers address and control inputs on the rising edge
of K, and registers data on the rising edge of K and the rising edge of K#. K# is ideally
180 degrees out of phase with K. All synchronous inputs must meet setup and hold times
around the clock rising edges.
Output Clock: This clock pair provides a user controlled means of tuning device output
data. The rising edge of C# is used as the output timing reference for first output data.
The rising edge of C is used as the output reference for second output data. Ideally, C# is
180 degrees out of phase with C. When use of K and K# as the reference instead of C
and C#, then fixed C and C# to HIGH. Operation cannot be guaranteed unless C and C#
are fixed to HIGH (i.e. toggle of C and C#)
R10DS0114EJ0200 Rev.2.00
Nov 09, 2012
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