PD46184182B_15 Datasheet, PDF (10/34 Pages) Renesas Technology Corp – 18M-BIT DDR II SRAM 2-WORD BURST OPERATION

μPD46184182B, μPD46184362B
Byte Write Operation
[μPD46184182B]
Operation
Write DQ0 to DQ17
Write DQ0 to DQ8
Write DQ9 to DQ17
Write nothing
K
L→H
−
L→H
−
L→H
−
L→H
−
K#
−
L→H
−
L→H
−
L→H
−
L→H
BW0#
0
0
0
0
1
1
1
1
BW1#
0
0
1
1
0
0
1
1
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
[μPD46184362B]
Operation
Write DQ0 to DQ35
Write DQ0 to DQ8
Write DQ9 to DQ17
Write DQ18 to DQ26
Write DQ27 to DQ35
Write nothing
K
L→H
−
L→H
−
L→H
−
L→H
−
L→H
−
L→H
−
K#
−
L→H
−
L→H
−
L→H
−
L→H
−
L→H
−
L→H
BW0#
0
0
0
0
1
1
1
1
1
1
1
1
BW1#
0
0
1
1
0
0
1
1
1
1
1
1
BW2#
0
0
1
1
1
1
0
0
1
1
1
1
BW3#
0
0
1
1
1
1
1
1
0
0
1
1
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# to BW3# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
R10DS0114EJ0200 Rev.2.00
Nov 09, 2012
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